The adoption of blockchain technology across financial, industrial, and IoT ecosystems has increased the demand for reliable and scalable consensus mechanisms. Traditional Practical Byzantine Fault Tolerance (PBFT) offers strong consistency and finality but scales poorly due to high message complexity and communication overhead. To address this, we propose Reliable Practical Byzantine Fault Tolerance (rPBFT), a consensus mechanism that improves performance and fault tolerance in large-scale distributed systems. rPBFT evaluates node reliability through message exchanges during consensus and dynamically forms a committee based on reliability scores. This reduces communication load, improves scalability, and prevents performance degradation caused by faulty nodes while maintaining decentralization without representative election. Experiments evaluated rPBFT against PBFT and HotStuff. In fault-free environments, PBFT achieved better performance due to the absence of reliability computation overhead. Under faulty conditions, rPBFT outperformed PBFT and HotStuff, achieving 30%–40% lower latency, 50%–80% higher throughput, and a 33% improvement in consensus success rate. In fault-tolerance tests, rPBFT maintained stable throughput as the Byzantine ratio and network fault ratio increased, demonstrating resilience via a reliability-based recovery model. These results confirm that rPBFT enhances scalability and robustness while preserving the core properties of Byzantine fault-tolerant consensus, making it well-suited for large-scale blockchain and IoT environments.

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8-b weight to 119.2 TOPS/W for 2-b weight.

Article Share on Policy-enforced linking of untrusted components Authors: Eunyoung Lee Princeton University, Princeton, NJ Princeton University, Princeton, NJView Profile , Andrew W. Appe Princeton University, Princeton, NJ Princeton University, Princeton, NJView Profile Authors Info & Claims ESEC/FSE-11: Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineeringSeptember 2003 Pages 371–374https://doi.org/10.1145/940071.940124Online:01 September 2003Publication History 5citation391DownloadsMetricsTotal Citations5Total Downloads391Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access