The networks considered in this paper consist of n identical combinational logic cells connected in cascade through bi-directional discrete information channels. All switching is done synchronously with unit time delay through each cell. Three classes of networks are formed according to whether or not information flow in one direction along the cascade is dependent upon that in the other. Steady-state behavioral relationships between the three classes are discussed, and the class having mutually dependent information flow is shown to be the only one which can exhibit steady-state memory properties. The main object of the paper is to derive several theorems concerning these memory properties. The last section interprets some previous results of Hennie as a start on the transients and cycling problems.

This paper concerns the analysis of recurrent-type, parity-check, error-correcting codes for memoryless, binary symmetric channels. These codes are defined to consist of message sequences augmented by insertions ofrsuccessive parity digits everybsuccessive message digits. An analysis framework is established for the codes which consists mainly of a parity check matrix[M]and a message difference vector[N]. Within this framework, a decoding scheme is developed which renders the codes capable of correcting any set of\eqslantless eerrors inm/bsuccessive(b + r)-digit blocks of coded message sequence, whereeis maximized over all parity-check codes having the same redundancy ratios and maximal lengths of dependence among their digits. An example is given of a linear-recurrent code which has a lower probability of error than the best comparable block code, and several outstanding problems are discussed.

The block diagram of an idealized over-all error-correcting digital computer is presented. This computer has the property that during each unit time interval, it can correct the effects of a specific maxium number of transient-type component failures which might occur anywhere within it. Yet, all its combinational logic circuitry is only of the error-detecting type. The corresponding reduction in equipment that this design feature makes possible is achieved at the expense of the computer's having to sit idle during a large percentage of those time intervals in which component failures occur. In a sense, therefore, the computer utilizes a great deal of time-domain redundancy as well as equipment-domain redundancy. This paper discusses some of the design requirements that are involved in using this type of redundancy structure.