The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead.>

Current state-of-the-art speech recognition systems are based on dynamic time warping (DTW) techniques in which the dominant computational task is input/reference word template matching and input/reference word non-linear time registration. A systolic array wafer scale architecture is presented which exploits the parallelism and local interconnect properties of this computation. The array executes either isolated or connected word recognition using either LPC or spectrally based templates. Restructurable VLSI (RVLSI) technology is being used to implement such an array comprised of 65 bit-serial arithmetic processing elements on a monolithic silicon 3" wafer. Speech recognition systems based on the RVLSI circuits are projected to be capable of supporting real-time vocabularies as large as 12,000 words.