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Anshu Aggarwal

dblp:28/2878 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% High-performance computing · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › shared memory
distributed shared memory
0.011998
Fine-Grain Software Distributed Shared Memory on SMP Clusters · HPCA 1998
Memory systems › shared memory › distributed shared memory
software distributed shared memory
0.011998
Fine-Grain Software Distributed Shared Memory on SMP Clusters · HPCA 1998
High-performance computing › cluster computing
SMP cluster
0.011998
Fine-Grain Software Distributed Shared Memory on SMP Clusters · HPCA 1998

Methods — techniques the papers use, named apart from their topics

race-free protocol · 0.0inline state checking · 0.0
YearPublicationVenuePosition
1998 Fine-Grain Software Distributed Shared Memory on SMP Clusters
abstract
Commercial SMP nodes are an attractive building block for software distributed shared memory systems. The advantages of using SMP nodes include fast communication among processors within the same node and potential gains from clustering where remote data fetched by one processor is used by other processors on the same node. This paper describes a major extension to the Shasta distributed shared memory system to run efficiently on a cluster of SMP nodes. The Shasta system keeps shared data coherent across nodes at a fine granularity by inserting inline code that checks the cache state of shared data before each load or store in an application. However allowing processors to share memory within the same SMP is complicated by race conditions that arise because the inline state check is non-atomic with respect to the actual load or store of shared data. We present a novel protocol that avoids such race conditions without the use of costly synchronization in the inline checking code. To characterize the benefits of using SMP nodes in the context of Shasta, we present detailed performance results for nine SPLASH-2 applications running on a cluster of Alpha multiprocessors.
Daniel J. Scales, Kourosh Gharachorloo, Anshu Aggarwal
HPCA3