A novel 64-bit hybrid radix-4 sparse-4 tree adder using clock-delayed (CD) footless domino logic is proposed. The adder operates at 6.4GHz with 181ps latency and it consumes 840mW at 1.2V in a standard 90nm CMOS technology. The adder latency is accurately measured by the programmable clock generated from delay-locked loop (DLL). Pseudo-exhaustive testing is applied so that all testable faults in this 64-bit adder are detected by just 23K patterns. This at-speed self testing technique is very useful for speed binning of high performance CPU.

A differential AC coupled transceiver for high-speed and low-swing has been implemented in a 0.18μm CMOS process. The proposed architecture includes a pulse receiver and a broadband limiting amplifier to recover a NRZ signal from a 75fF capacitive coupled channel. The system works at 12Gb/s through 10cm FR4 printed circuit board interconnect, while dissipating only 13.5mW with a bit error rate less than 10-12.

In this paper, we consider the constructions of anN-to-Koptical priority queue with buffer Σi=1Mdiby using a feedback system consisting of a single (M+max[N,K]) × (M+max[N,K]) (bufferless) optical crossbar switch, min[N,K] 1× 2 (bufferless) optical crossbar switches, andMfiber delay lines with delaysd1,d2,...,dM, where N is the number of arrival links and K is the number of departure links of the priority queue. We first obtain two sufficient conditions [the conditions (A1) and (A2) in Section I] for our constructions ofN-to-Koptical priority queues. By establishing a space-time advancement property and a monotonically decreasing/increasing property for the packets stored in the fiber delay lines, we then use these sufficient conditions to show that with an appropriate choice for the delaysd1,d2,...,dM, we can achieve a buffer size ofO([(M3/N2)]) for the case thatN=K. For the special case thatN=K=1, our constructions achieve a buffer size ofO(M3), which is much better than theO(M2) buffer size previously known in the literature for single-input single-output optical priority queues. Therefore, other than the extension from the constructions of optical priority queues with a single input and a single output to the constructions of optical priority queues with multiple inputs and multiple outputs, our constructions also achieve a larger buffer size than previous constructions of single-input single-output optical priority queues. Furthermore, we give another sufficient condition [the condition (A3) in Section I] for our constructions ofN-to-Koptical priority queues and then use that condition to obtain choices for the delaysd1,d2,...,dMso that our constructions have the fault tolerant capability that can tolerate up toFbroken/malfunctioning fibers (e.g., fiber cut, fiber shorting out, etc.), where 0 ≤F≤M-1.

In this paper, we consider the construction of an optical priority queue with a single (M+1)times(M+1) switch and M fiber delay lines. The M fiber delay lines are connected from M outputs of the switch back to M inputs of the switch, leaving one input (resp. output) of the switch for the input (resp. output) of the priority queue. It was known that with an appropriate choice of the lengths of the delay lines, such a construction can be used for exact emulation of an optical priority queue with O(M2) buffer size. In this paper, we show that the buffer size can be further extended to O(M3) using the same construction. The improvement relies on establishing a partial ordering for all the packets stored in the delay lines.