This presentation explains some of the challenges of SPICE in simulating circuits with nano-devices and proposes a circuit simulation approach that allows multidimensional and multi-parameterized device physical equations to be easily included in a circuit simulator.

This paper presents a method for deriving circuit model stamp equations from the characteristic equations of multiterminal devices. The method is applied to the derivation of stamp equations of carbon nanotube and graphene nano-ribbon field-effect transistors (FETs) for use in general-purpose circuit simulators. We first review existing methods of modeling FETs for circuit simulation and point out some of the weaknesses in these models. We then explain how to derive model equation stamps directly from the device physical characteristic equations without the need of eliminating internal device variables and without having to construct equivalent circuits consisting of interconnections of two-terminal resistors, controlled sources, and two-terminal capacitors.

This paper presents an extension to the popular nodal and modified nodal formulation methods that allows elements whose characteristic functions include controlling variables, in addition to voltages and currents, other variables, such as charge, flux, and other physical parameters, to be included in the circuit equation formulation in a straightforward manner. Stamps, similar to nodal and modified nodal circuit element stamps, are developed to include these elements in the circuit matrix equation without the need of deriving equivalent circuit models consisting of interconnections of elements characterized only by currents and voltages, as in the current practice. The method is applied to derive circuit stamps of memristive, memcapacitive, meminductive, and other complex device models. The method reduces the size of the overall circuit matrix and allows easy model evaluation and linearization during the circuit iterative solution process.

Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic postroute gate-sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high-performance designs.

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.

One of the critical challenges in today's high-performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools are effective at analyzing and identifying noise in the postroute design stage when detailed parasitic information is available. However, noise problems identified at this stage of the design cycle are very difficult to correct due to the limited flexibility in design and may cause additional iterations of routing and placement which adds costly delays in its time to market. In this paper, we introduce a probabilistic preroute noise analysis approach to identify postroute noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances, and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design are not yet available, we propose a novel probabilistic method for capacitance extraction. We present results on two high-performance microprocessors in 0.18 /spl mu/m technology that demonstrate the effectiveness of the proposed approach.

Noise estimation and avoidance are becoming critical, 'must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise model which contains as many driver/interconnect parameters as possible, is necessary for any sensitivity based noise avoidance approach. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width as well as sensitivities to all model parameters. We then use them model parameter sensitivities to analyze and evaluate various noise avoidance techniques such as driver sizing, wire sizing, wire spacing and layer assignment. Both our model and noise avoidance evaluations are verified using realistic circuits in 0.13/spl mu/ technology. We also present effectiveness of discussed noise avoidance techniques on a high performance microprocessor core.

In this article, we present a simulation-based technique for estimation of signal statistics (switching activity and signal probability) at the flip-flop output nodes (state signals) of a general sequential circuit. Apart from providing an estimate of the power consumed by the flip-flops, this information is needed for calculating power in the combinational portion of the circuit. The statistics are computed by collecting samples obtained from fast RTL simulation of the circuit under input sequences that are either randomly generated or independently selected from user-specified pattern sets. An important advantage of this approach is that the desired accuracy can be specified up front by the user; with some approximation, the algorithm iterates until the specified accuracy is achieved. This approach has been implemented and tested on a number of sequential circuits and has been shown to handle very large sequential circuits that can not be handled by other existing methods, while using a reasonable amount of CPU time and memory (the circuit s38584.1, with 1426 flip-flops, can be analyzed in about 10 minutes).

We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24%, respectively, over dual-output domino and a 48% power reduction for the largest circuit.

This paper presents techniques to include the effect of supply voltage noise on the circuit propagation delay of a digital VLSI circuit. The proposed methods rely on an input-independent approach to calculate the logic gate's worst-case power supply noise. A quasi-static timing analysis is then applied to derive a tight upper-bound on the delay for a selected path with power supply noise effects. This upper-bound can be further reduced by considering the logic constraints and dependencies in the circuit. Experimental results for ISCAS-85 benchmark circuits are presented using the techniques described in the paper. HSPICE simulation results are also used to validate our work.

Article Share on Maximum voltage variation in the power distribution network of VLSI circuits with RLC models Authors: Sudhakar Bobba Sun Microsystems Inc., 901 San Antonio Road, M/S: USUN02-301, Palo Alto, CA Sun Microsystems Inc., 901 San Antonio Road, M/S: USUN02-301, Palo Alto, CAView Profile , Ibrahim Hajj Department of ECE, American University of Beirut, Beirut, Lebanon Department of ECE, American University of Beirut, Beirut, LebanonView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 376–381https://doi.org/10.1145/383082.383186Online:06 August 2001Publication History 5citation262DownloadsMetricsTotal Citations5Total Downloads262Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper, we present high-performance bidirectional repeaters that recondition the signal waveform and reduce the signal degradation. We also present the application of these repeaters to the design of high-performance bidirectional busses. SPICE simulation results for long bidirectional interconnects show an almost linear increase in delay with repeaters compared to a quadratic increase in delay without repeaters. These repeaters are also applied to improve the performance of long AND domino gates. SPICE simulation results show a significant reduction in the delay of long AND domino gate with repeaters.

Estimates of the peak power dissipation and the peak current are required in the design of reliable VLSI circuits. The peak current current drawn by a digital filter is dependent on the filter coefficients and the inputs to the multipliers in the filter. This input dependence makes the estimation of peak current for a digital filter a hard problem. We present a technique to estimate the maximum current drawn by a digital filter. The approach consists of: (1) building peak current macro-models for multipliers in terms of the input data transitions and the coefficient, and (2) using these models in a graph based formulation for finding the peak current of the digital filter. The peak current macro-models for multipliers are validated by comparisons with SPICE simulations. We also present the application of the technique for estimating the peak current of digital filters in a 51.84 Mb/s 16-CAP receiver.

In this paper, we present simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

In this paper, we present low-power and high-performance logic gates called the current-mode threshold logic (CMTL) gates. Low-power dissipation is achieved by limiting the voltage swing on the interconnects and the internal nodes of the CMTL gates. High-performance is achieved by the use of transistor configurations that sense a small difference in current and set the differential outputs to the correct values. The realization of NAND, NOR, AND, OR logic gates and other logic functions using the CMTL gates is presented. We also present several implementations of CMTL gates and describe the relative advantages and limitations of these implementations. SPICE simulation, results for a 1.5 V 0.18 u CMOS technology are also presented for the different circuit configurations described in the paper.

The memory hierarchy of high-performance and embedded processors has been shown to be one of the major energy consumers. For example, the Level-1 (L1) instruction cache (I-Cache) of the StrongARM processor accounts for 27% of the power dissipation of the whole chip, whereas the instruction fetch unit (IFU) and the I-Cache of Intel's Pentium Pro processor are the single most important power consuming modules with 14% of the total power dissipation [2]. Extrapolating current trends, this portion is likely to increase in the near future, since the devices devoted to the caches occupy an increasingly larger percentage of the total area of the chip. In this paper, we propose a technique that uses an additional mini cache, the LO-Cache, located between the I-Cache and the CPU core. This mechanism can provide the instruction stream to the data path and, when managed properly, it can effectively eliminate the need for high utilization of the more expensive I-Cache. We propose, implement, and evaluate five techniques for dynamic analysis of the program instruction access behavior, which is then used to proactively guide the access of the LO-Cache. The basic idea is that only the most frequently executed portions of the code should be stored in the LO-Cache since this is where the program spends most of its time. We present experimental results to evaluate the effectiveness of our scheme in terms of performance and energy dissipation for a series of SPEC95 benchmarks. We also discuss the performance and energy tradeoffs that are involved in these dynamic schemes. Results for these benchmarks indicate that more than 60% of the dissipated energy in the I-Cache subsystem can be saved.

In this paper, we focus on low-power design techniques for high-performance processors at the architectural and compiler levels. We focus mainly on developing methods for reducing the energy dissipated in the on-chip caches. Energy dissipated in caches represents a substantial portion in the energy budget of today's processors. Extrapolating current trends, this portion is likely to increase in the near future, since the devices devoted to the caches occupy an increasingly larger percentage of the total area of the chip. We propose a method that uses an additional minicache located between the I-Cache and the central processing unit (CPU) core and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly simplify the required hardware, eliminate unnecessary instruction fetching, and consequently reduce signal switching activity and the dissipated energy. We show that the additional cache, dubbed L-Cache, is much smaller and simpler than the I-Cache when the compiler assumes the role of allocating instructions to it. Through simulation, we show that for the SPECfp95 benchmarks, the I-Cache remains disabled most of the time, and the "cheaper" extra cache is used instead. We also propose different techniques that are better adapted to nonnumeric nonloop-intensive code.

Accurate simulation of interconnect effects is an increasingly critical step in high speed deep submicron design. With ever increasing frequency of digital/analog signals, the traditional lumped RC elements may not be accurate enough in modeling RC interconnects in VLSI applications due to the distributed nature of realistic interconnects. In this paper a novel analytic time-domain model for distributed RC interconnects is developed for application in nonlinear circuit simulators. The exact analytical solution is derived under the assumption of piecewise-linear signal waveforms at the two ports of the line. We have incorporated this model into a general purpose circuit simulator using the SWEC technique.

Energy dissipated in on-chip caches represents a substantial portion in the energy budget of today's processors. Extrapolating current trends, this portion is likely to increase in the near future, since the devices devoted to the caches occupy an increasingly larger percentage of the total area of the chip. We extend the work proposed by J. Kin et al. (1997), in which an extra, small cache (called filter cache) is inserted between the CPU data path and the L1 cache and serves to filter most of the references initiated from the CPU. In our scheme, the compiler is used to generate code that exploits the new memory hierarchy and reduces the possibility of a miss in the extra cache. Experimental results across a wide range of SPEC95 benchmarks show that this cache, which we call L-Cache, has a small performance overhead with respect to the scheme without any extra caches, and provides substantial energy savings. The L-Cache is placed between the CPU and the I-Cache. The D-Cache subsystem is not modified. Since the L-Cache is much smaller, and thus, has a smaller access time than the I-Cache, this scheme can also be used for performance improvements provided that the hit rate in the L-Cache is very high. In our experimental results, we show that the L-Cache does indeed improve performance in some cases.

Article Using dynamic cache management techniques to reduce energy in a high-performance processor Share on Authors: Nikolaos Bellas Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, ILView Profile , Ibrahim Hajj Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, ILView Profile , Constantine Polychronopoulos Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, ILView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 64–69https://doi.org/10.1145/313817.313856Online:17 August 1999Publication History 59citation448DownloadsMetricsTotal Citations59Total Downloads448Last 12 Months6Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Dynamic logic circuits [2] are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. One well-known dynamic logic family is the domino CMOS family, which, however, su ers from its inability to

With the increase in the complexity of VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a method for multiple design error diagnosis and correction. Our approach uses the results of test vector simulation for both error detection and error correction. This makes it applicable to circuits with no global BDD representation. In addition, diagnosis is performed through an implicit enumeration of potentially erroneous lines in an effort to avoid the exponential explosion of the error space. Experimental results on ISCAS'85 benchmark circuits show that our approach can typically detect and correct 1, 2 and 3 errors within seconds of CPU time.

With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.

This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f/sub 1/. Next, a variant of entropy coding function f/sub 2/ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f/sub 1/ and f/sub 2/ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 /spl mu/m CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes.

Transitions on high-capacitance buses in very large scale integration systems result in considerable system power dissipation. Therefore, various coding schemes have been proposed in the literature to encode the input signal in order to reduce the number of transitions. In this paper, we derive lower and upper bounds on the average signal transition activity via an information-theoretic approach, in which symbols generated by a process (possibly correlated) with entropy rate H are coded with an average of R bits per symbol. The bounds are asymptotically achievable if the process is stationary and ergodic. We also present a coding algorithm based on the Lempel-Ziv data-compression algorithm to achieve the bounds. Bounds are also obtained on the expected number of ones (or zeros). These results are applied to determine the activity-reducing efficiency of different coding algorithms such as, entropy coding, transition signaling, and bus-invert coding, and determine the lower bound on the power-delay product given H and R. Two examples are provided where transition activity within 4% and 9% of the lower bound is achieved when blocks of eight symbols and 13 symbols, respectively, are coded at a time.

Programmable logic array (PLA) is a circuit realization for the two-level sum of products representation of a multi-output Boolean function. The current drawn by a PLA is input dependent and it makes the problem of estimating the maximum current intractable. Integrated circuit reliability and signal integrity are related to the maximum current drawn by the circuit. Hence, an estimate of the maximum current is required for the design of a reliable VLSI circuit. In this paper, we present an input pattern-independent algorithm to obtain the estimate of maximum and minimum currents drawn by a PLA over all possible input vectors. Experimental results on several benchmark circuits and comparisons with exhaustive simulations are also included in this paper.

In this paper we propose a technique that uses an additional mini cache located between the I-Cache and the CPU core, and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly simplify the required hardware, eliminate unnecessary instruction fetching, and consequently reduce signal switching activity and the dissipated energy.

Presented in this paper are decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in adaptive filters. The coefficients generated by the weight update block in an adaptive filter are passed through a decorrelating block such that fewer bits are required to represent the coefficients. Thus, the size of the arithmetic units in the filter (F-block) is reduced thereby reducing the power dissipation. The DECOR transform is well suited for narrow-band filters because there is significant correlation between adjacent coefficients. In addition, the effectiveness of DECOR transforms increases with increase in the order of the filter and decrease in coefficient precision. Simulation results indicate reduction in power dissipation in the F-block ranging from 12% to 38% for filter bandwidths ranging from 0.15 ƒs to 0.025 ƒs (where ƒs is the sample rate).

In this p ap er we pr esent an inputpattern independent method to compute the maximum current envelope, which is an upper bound over all possible curr ent waveforms drawn by a circuit. The maximum current envelope can be used to compute the worst-c ase RMS current and average cur rent dr awn by a set of gates. These current values can be used in the design of the p ower bus to ensure that the power bus interconne cts are not susc eptible to ele ctromigration (EM) induced failur e. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.

Presented here is an analytical methodologyto determine the average signal activity, T, from the high-levelsignal statistics, a statistical signal generation model,and the signal encoding.Simulation results for 16 bit signalsgenerated via AR(1) and MA(1) models indicate anestimation error in T of less than 2%.The applicationof the proposed method to the estimation of T in DSPhardware is also explained.

With the increase in the complexity of VLSI circuit design and the corresponding increase in the number of logic gates on a chip, logic design errors can frequently occur. In this paper we present an efficient approach to Design Error Detection and Correction when a small number of modifications can rectify the design. Our method is based on test vector simulation and Boolean function manipulation techniques. The proposed approach guarantees to return a solution, if such a solution exists in our modification model, in a short computational time. Experimental results show the robustness of our approach.

In this paper we describe GOLDENGATE-a bridging fault simulator for cell-based digital VLSI circuits with the following features: 1. It targets both combinational and sequential circuits. 2. It simulates general (routing, adjacency, and intra-cell) realistic bridging faults efficiently through a table-based scheme. The pre-computed table contains accurate cell output voltage and I/sub DDQ/ values obtained through electrical-level simulations. 3. It simulates both feedback and nonfeedback bridging faults (BFs) efficiently through a cycling event-driven technique. 4. It allows mixed voltage and I/sub DDQ/ simulation to support a fully hybrid test scheme where mixed logic and I/sub DDQ/ sensings are allowed. The experimental results show that GOLDENGATE is both accurate and fast.

Transitions on high capacitance busses in VLSI systems result in considerable system power dissipation. Therefore, various coding schemes have been proposed in the literature to encode the input signal in order to reduce the number of transitions. In this paper we derive achievable lower and upper bounds on the expected signal transition activity. These bounds are derived via an information-theoretic approach in which symbols generated by a source (possibly correlated) with entropy rate H are coded with an average of R bits/symbol. These results are applied to, (1) determine the activity reducing efficiency of different coding algorithms such as Entropy coding, Transition coding, and Bus-Invert coding, (2) bound the error in entropy-based power estimation schemes, and (3) determine the lower-bound on the power-delay product. Two examples are provided where transition activity within 4% and 8% of the lower bound is achieved when blocks of 8 and 13 symbols respectively are coded at a time.

Presented in this paper is a novel methodology to determine the average number of transitions in a signal from its word-level statistical description. The proposed methodology employs: (1) high-level signal statistics, (2) a statistical signal generation model, and (3) the signal encoding (or number representation) to estimate the transition activity for that signal. In particular, the signal statistics employed are mean (/spl mu/), variance (/spl sigma//sup 2/), and autocorrelation (/spl rho/). The signal generation models considered are autoregressive moving-average (ARMA) models. The signal encoding includes unsigned, one's complement, two's complement, and sign-magnitude representations. First, the foilowing exact relation between the transition activity (t/sub i/), bit-level probability (p/sub i/), and the bit-level autocorrelation (/spl rho//sub i/) for a single bit signal b/sub i/ is derived: t/sub i/=2p/sub i/(1-p/sub i/)(1-/spl rho//sub i/) (1). Next, two techniques are presented which employ the word-level signal statistics, the signal generation model, and the signal encoding to determine /spl rho//sub i/ (i=0, /spl middot//spl middot//spl middot/, B-1) in (1) for a B-bit signal. The word-level transition activity T is obtained as a summation over t/sub i/ (i=0,/spl middot//spl middot//spl middot/, B-1); where t/sub i/ is obtained from (1). Simulation results for 16-bit signals generated via ARMA models indicate that an error in T of less than 2% can be achieved. Employing AR(1) and MA(10) models for audio and video signals, the proposed method results in errors of less than 10%. Both analysis and simulations indicate the sign-magnitude representation to have lower transition activity than unsigned, ones' complement, or two's complement. Finally, the proposed method is employed in estimation of transition activity in digital signal processing (DSP) hardware. Signal statistics are propagated through various DSP operators such as adders, multipliers, multiplexers, and delays, and then the transition activity T is calculated. Simulation results with ARMA inputs show that errors less than 4% are achievable in the estimation of the total transition activity in the filters. Furthermore, the transpose form structure is shown to have fewer signal transitions as compared to the direct form structure for the same input.

This paper presents a technique to correct multiple logic design errors in a gate-level netlist. A number of methods have been proposed for correcting single logic design errors. However, the extension of these methods to more than one error is still very limited. We direct our attention to circuits with a low multiplicity of errors. By assuming different error dependency scenarios, multiple errors are corrected by repeatedly applying a single error search and correction algorithm. Experimental results on correcting double-design errors and triple-design errors on ISCAS and MCNC benchmark circuits are included.

An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. An adaptive genetic algorithm (GA) is used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that GA-based test generators are very well suited for generating compact test sets for I/sub DDQ/ testing of bridging faults.

In this paper, a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates a circuit to determine the critical transistors that are most susceptible to hot-carrier effects (HCEs). It then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE-induced performance degradation. Two criteria are used to evaluate HCE degradation. The first criterion is the estimation of local damage in each transistor, which indicates the possibility of failure of individual devices. The second criterion is the global degradation of the circuit, namely the increase of delay in digital circuits. If either criterion exceeds a user-specified limit, several alternative circuit redesign strategies can be chosen by the user from a suggested menu. Based on this choice, the system will automatically redesign the critical parts of the circuit to improve circuit performance. The advantages and disadvantages of these alternative redesign strategies are also compared.

A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified up-front by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 flip-flops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flip-flops). I. INTRODUCTION The dramatic decrease in feature size and the corresponding increase in the number of devices on a chip, combined with the growing demand for portable communication and computing systems, have made power consump...

A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Experimental results show that by formulating gate size selection together with the clock skew optimization as a single optimization problem, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. Finally, we address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.>

Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits.>

The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary in this paper) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using mixed-mode gate- and electrical-level detection methods, good diagnostic capability is achieved using only gate-level generated test sets. Second, we evaluate two reduced fault dictionaries, the pass/fail dictionary and the count dictionary. Finally, the effectiveness of I/sub DDQ/ for diagnosis is examined. The results show that I/sub DDQ/, combined with the proposed voltage detection methods, achieves the highest diagnostic performance, with nearly complete diagnosis.>

In this paper, we rst present an e cient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure isembedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As aresult, the algorithm is able to obtain superior solutions. 1

Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade both design reliability and performance. Maximum current estimates are needed in the circuit to accurately determine the impact of these problems. In a previous paper by the authors (see Design Automation Conf., p. 2-7, June 8-12, 1992), a pattern-independent, linear time algorithm (iMax) is described that is very effective in estimating the maximum current waveforms at various contact points in the circuit. In the aforementioned paper, the algorithm was demonstrated for simple gate delay and current models. In this paper, we first derive expressions for modeling delays and current waveforms for a general gate and then describe how the algorithm can be extended under more general models.>

The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using detection methods good diagnostic capability is achieved using only gate-level generated test sets. Second, the authors evaluate two reduced fault dictionaries, the pass/fail dictionary and the count dictionary. The results show the performance of the much smaller pass/fail dictionary is nearly equal to the full dictionary. Third, the effectiveness of I/sub DDQ/ for diagnosis is examined. The results show that I/sub DDQ/ combined with the proposed voltage detection methods achieves the highest diagnostic performance, with near complete diagnosis.>

In this paper, a new approach is presented for estimating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user-specified deterministic input waveforms are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.>

Logic verification tools are often used to verify a gate-level implementation of a digital system in terms of its functional specification. If the implementation is found not to be functionally equivalent to the specification, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect gate-level implementation. We use Boolean equation techniques to search for potential error locations. An efficient search and pruning algorithm is developed by introducing the notion of immediate dominator set. Two correction procedures are proposed. Gate correction corrects errors such as wrong gate type, missing inverters, etc.; line correction corrects errors such as missing wires and wrong connections. Our method is robust and covers all, simple design errors described by Abadir et al. (1988). Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques.>

Article Diagnosis and correction of logic design errors in digital circuits Share on Authors: Pi-Yu Chung View Profile , Yi-Min Wang View Profile , Ibrahim N. Hajj View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 503–508https://doi.org/10.1145/157485.165003Online:01 July 1993Publication History 61citation264DownloadsMetricsTotal Citations61Total Downloads264Last 12 Months3Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

: Currents flowing in the power and ground (P&G) lines of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Maximum current estimates are therefore needed in the P&G lines to determine the severity of the voltage drop problems and to properly design the supply lines to eliminate these problems. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible inputs, this problem has, for a long time, remained largely unsolved. In [1], we proposed a pattern-independent, linear time algorithm (iMax) that estimates an upper bound envelope of all possible current waveforms that result from the application of different input patterns to the circuit. While the bound produced by iMax is fairly tight on many circuits, there can be a significant loss in accuracy due to correlations between signals internal to the circuit. In this paper, we present ...

Probabilistic simulation has been shown to be a very cost-effective approach to the computation of voltage and current waveform statistics in CMOS digital circuits, compared to exhaustive simulation.Thk approach is particularly attractive when long-term reliability issues such as electromigration, hot-carrier effects, and average power, are to be estimated over all possible input signals.In this paper we present new algorithms for performing probabilistic simulation that provide significant improvements over existing ones, both in accuracy and speed.The improvements are carried out at the subcircuit level,where the statistics of the current and voltage waveforms and the delays are computed more accurately, and at the global level, where signal correlations are considered.The new algorithms have been implementedin a computer program and tested on a number of large benchmark circuits.I.

This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standard-cell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Traditional methods treat these two problems separately, which may lead to very sub-optimal solutions in some cases. Experimental results show that by considering the two problems together, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

In this paper a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates circuits to determine the critical transistors that are most susceptible to hot-carrier effects (HCE); it then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE degradation on the performance. The advantages and disadvantages of these alternative designs are also compared.>

A method for switch-level timing simulation of bipolar emitter-coupled-logic (ECL) circuits is presented. The approach is based on the development of a switch level model of the transistor and on the representation of the circuit by a switch-graph. The circuit is partitioned into subcircuits, and the symbolic logic expressions, which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions, are then generated. Timing information is computed using a new physical delay model based on device equations, transistor interconnection, input slew rate, and loading conditions. The delay model was derived on the basis of average branch current analysis and incorporates more than 15 delay-sensitive circuit and SPICE BJT model parameters. The use of a novel parametric correction scheme permits greater freedom to handle complex effects such as high-level injection, parasitic resistances, and interconnection delay. In addition, the dynamic fanout effects due to base leakage current are incorporated by a fanout collapsing technique.>

An approach for estimating hot-carrier induced degradation in MOS transistor circuits is presented. The approach uses probabilistic timing simulation techniques to estimate the cumulative effects of all possible inputs on hot-carrier effect (HCE) degradation in each transistor in the circuit in a single run rather than using exhaustive or Monte Carlo simulations. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.>

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Describes an approach for performing transistor-level logical fault simulation of VLSI MOS circuits. The method is based on a recently introduced algebraic approach to switch-level simulation. The faults considered are grouped into four sets: node stuck-at, transistor stuck-open, transistor stuck-on, and bridging faults. The authors consider concurrent fault simulation implementation, and compare, using typical examples, the computational and storage requirements of including all faults in the fault list in one simulation run versus using multiple runs with different fault groupings. Both output voltage and supply current monitoring are used for fault detection.>

The authors describe a method for performing transistor-level logical fault simulation. The method relies on switch-level modeling and uses a switch-level matrix-equation formulation and solution into which fault models are inserted in a straightforward manner. The fault models include transistor stuck-at, node stuck-at, and bridging faults. Both output voltage monitoring and current testing are used for fault detection. The approach has been implemented in a concurrent fault simulator and tested using both combinational and sequential circuit benchmarks. The results of the simulator compare very favourably with existing switch-level fault simulators while allowing more complete transistor-level fault models to be included.>

The probabilistic simulation approach is extended to include the computation of the variance waveform of the power/ground current, in addition to its expected waveform. The focus is on the problem of estimating the median time-to-failure (MTF) due to electromigration (EM) in the power and ground buses of CMOS circuits. Theoretical results that quantify the relationship between the MTF and the statistics of the stochastic current are presented. This leads to a more accurate estimate of the MTF that requires both the expected and variance waveforms. A novel technique is then presented to compute the variance waveform for CMOS circuits, which has been incorporated into the probabilistic simulator CREST. Results of this implementation demonstrating efficiency and accuracy on a number of circuits are provided. The authors use these results to study the importance of the variance waveform by estimating its contribution to the MTF relative to that of the expected waveform.>

A methodology is presented for computing the steady-state solution of switch-level networks. The method is based on a matrix algebra similar in many respects to circuit nodal analysis. The formulation steps are similar to the nodal equation formulation steps and the network matrix has the same dimension and structure as the nodal admittance matrix, except that logic operations (min and max operations) are used in formulating and solving the network equations. Solution algorithms are then developed using the new algebra. The approach has been implemented as a part of a mixed-mode simulator which uses partitioning and sparse matrix solution techniques in analyzing a circuit. In its switch-level mode, the simulator can perform logic and concurrent fault simulation using realistic fault models, including bridging faults, and has been found to be competitive with existing switch-level simulators.>

A novel gate-level high-speed VLSI logic simulation technique with assignable delay is presented that uses bitwise logic operations together with the segmented waveform relaxation method (SWRM). The implementation of the technique on parallel computers is described. Although the proposed technique is similar to the compiled-code method, it does not generate a compiled-code and can handle different delay methods which cannot be handled by the conventional compiled-code method. By using waveform relaxation techniques, the simulation can always find the correct logic level in tightly coupled feedback circuits (such as flip-flops), while event-driven simulation may not give the correct logic levels in these cases. The proposed simulator reduces the memory requirements and computation time by using segmented waveform relaxation. On a single processor the simulator is about one order of magnitude faster than the traditional event-driven simulators and can easily handle tens of thousands of gates.>

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented.>

Consideration is given to the fault detection problem for a single fault in a single MOS channel-connected subcircuit. The following three decision subproblems are identified: (1) decide if a test vector exists, (2) decide if an initializing vector exists, and (3) decide if a test pair is robust. It is proven that each of these problems is NP-complete. More importantly, it is proved that the first two remain NP-complete for the simplest subcircuit design styles, namely series/parallel nMOS or CMOS logic gates. The third subproblem is shown to be of linear complexity for a CMOS logic gate with a stuck-open fault. It is illustrated that a test pair that is not robust may contain a robust subtest pair, and a necessary and sufficient condition for this to happen in CMOS logic gates is given. This leads to a linear time algorithm for CMOS logic gates which tests for robustness and, if possible, derives a robust test pair from a possibly nonrobust pair. The implications of these complexity results on practical transistor-level test generation tools are discussed.>

An automatic module generation system is presented which is based on the metal-metal matrix layout style for double-metal CMOS technology. The circuit is described in SPICE format or by incidence matrices. The transistor circuit is partitioned into medium-sized cell containing up to 200 transistors and converted into physical mask layers using a cell generator. This generator has been designed to control the height of the cells and hence also the width, so that the cells can be used in a standard cell layout environment. The height of the cell is controlled by removing vertical constraints imposed on horizontal nets by adding additional columns to the cell.>

A novel technique for deriving the variance waveform for CMOS circuits is presented. Using this technique, the authors establish the importance of the variance waveform by showing that its contribution to the mean-time-to-failure estimate can be in the range of 100% to 200% relative to that of the expected waveform. The technique has been built into the probabilistic simulator CREST and has shown good agreement with SPICE, as well as excellent speedup.>

A novel technique is introduced for automatically performing mixed-mode timing simulation of MOS circuits. A SPICE2 circuit description is assumed to be given, the circuit is first partitioned into channel-connected subcircuits. Each subcircuit is then examined and is statically classified as digital or analog if one of many configurations is detected. Subcircuits which contain memory cells, sense amplifiers, or internal feedback are automatically classified as analog. Any user-specified analog subcircuits are classified as analog. Analog subcircuits are simulated using detailed electrical simulation while digital subcircuits are simulated using fast timing simulation with a ramp waveform representation. Fast timing simulation uses a nonlinear macromodel to model the charging and discharging of subcircuit output nodes. State transitions are initially modeled using a single ramp. Static and dynamic mode selection are used to ensure that accuracy is retained during simulation while minimizing simulation time. The implementation of these techniques in IDSIM2 is discussed. Examples of automatic mixed-mode timing simulation are presented.>

The estimation of the median time-to-failure (MTF) due to electromigration in the power and ground buses of VLSI circuits is addressed. In their previous work (Proc. 25th ACM/IEEE Design Autom. Conf., p.294-9, 1988), the authors presented a novel technique for MTF estimation based on a stochastic current waveform model. They derived the mean (or expected) waveform (not a time average) of such a current model and conjectured that it is the appropriate current waveform to be used for MTF estimation. The authors prove that conjecture and present new theoretical results which show the exact relationship between the MTF and the statistics of the stochastic current. This leads to a more accurate technique for deriving the MTF which requires the variance waveform of the current, in addition to its mean waveform. The authors then show how the variances of the bus branch currents can be derived from those of the gate currents, and describe several simplifying approximations that can be used to maintain efficiency and, therefore, make possible the analysis of VLSI circuits.>

A fault simulation algorithm based on the partitioning of faults into groups, with the group size equal to the number of bits in the host computer word, is presented. The fault effects of a particular group are evaluated using parallel fault simulation techniques and propagated using concurrent fault simulation techniques. The speed of the algorithm depends on the circuit and on the fault-grouping criterion. Three static grouping criteria are examined and compared in terms of speed and memory requirements. A dynamic regrouping technique is developed and is shown to improve the performance of static grouping.>

A novel, systematic approach to sequential MOS circuit design is described. The approach aims at minimizing the number of transistors needed to implement a given switching function. The techniques used are based on the switching network logic (SNL) approach, which was previously introduced as a systematic method of designing MOS combinational logic circuits. The authors extend the approach to sequential MOS circuit design. Examples are given to show that the proposed method reduces the number of MOSFETs as compared to existing design methods. A CAD (computer-aided design) program based on the SNL approach is presented as a finite state machine generator.>

A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported.>

CREST is a pattern-independent current estimation approach developed to support electromigration analysis tools. It uses the powerful, original concept of probabilistic simulation to generate accurate estimates of the expected current waveforms efficiently. The original implementation of CREST is extended to circuits containing pass transistors, reconvergent fanout, and feedback, and heuristics to simulate circuits with large reconvergent fanout or feedback blocks efficiently are provided. The results of using CREST on several real circuits are presented.>

The approach accounts for RC parasitic loading, overlapping inputs, and incomplete charging or discharging of output nodes. The macromodeling splits the subcircuits data into transistor-gate information and loading information. In a given design many subcircuits have identical gate configurations, but each instance of a gate has a unique RC loading condition. During simulation the gate and loading information is combined and used to calculate output-node voltage changes. All necessary information needed for voltage calculations are precomputed and stored in tables. The proposed macromodeling and the delay method greatly reduce simulation time. The approach has been implemented in a simulator called IDSIM2, and a number of large examples have been simulated. Speedups of up to three orders of magnitude have been obtained compared to standard circuit simulation, with loss of accuracy of less than 10%.>

iEDISON optimizes the transistor sizes of a circuit so that its performance is least sensitive to manufacturing process fluctuations. iEDISON considers three methods for design optimization, namely, the response surface method, the Taguchi method, and the nonnested experimental design method. These methods use experimental designs and regression models to explore the statistical performance variations. The efficiency of the system is demonstrated by an example on clock-skew minimization.>

This paper describes a new approach for logic simulation of bipolar digital circuits. The approach is based on the development of a switch-level model of the transistor and on representing the circuit by a switch-graph. The method automatically partitions the circuit into subcircuits, and symbolic logic expressions are then generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. The method thus extracts a gate-level functional description of the circuit from transistor netlist or layout. Logic and fault simulation can then be performed using either extracted logic expressions or the switch-graph model. The approach has been implemented in a computer program for logic simulation of common-mode logic (CML) bipolar circuit designs.