Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented. 2.

The circuit techniques used to implement a 600 MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4 GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a variety of static and dynamic design methods balanced critical path delays against power consumption. The chip relies heavily on full custom design and layout to meet speed and area goals. An extensive CAD suite guaranteed the integrity of the design.

Static timing verification on a large full-custom design isan extremely challenging problem for which no complete solution exists.In this paper, we present our experience on the timing verification of our next generation CMOS CPU design using an internally developed tool, NTV.The entire chip, which consists of 1.2M transistors and 500K nodes, has been verified by NTV in less than 7 CPU hours on a VAX-8800.42K timing constraints were verified and 350K signal paths were traced.Among the reported critical paths, 85% were already known to designers and the remaining 15'%0were unforeseen critical paths.