Demo Data from EDBT 2026 / reviewers in the wild / expert
Francisco J. Mora
dblp:28/4225
· DBLP profile ↗
5ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Security and privacy · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Interconnection networks and networks-on-chip · 76% High-performance computing · 24% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
High-performance computing
collective communication |
0.1 | 2 | 2009 | Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009 Scalable Hardware-Based Multicast Trees · SC 2003 |
Interconnection networks and networks-on-chip › multicast
hardware multicast |
0.1 | 2 | 2009 | Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009 Scalable Hardware-Based Multicast Trees · SC 2003 |
Interconnection networks and networks-on-chip › network topology › tree networks
fat-tree network |
0.1 | 1 | 2009 | Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009 |
Interconnection networks and networks-on-chip › routing algorithms
fault-tolerant routing |
0.1 | 1 | 2009 | Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009 |
Interconnection networks and networks-on-chip › routing algorithms
multicast routing |
0.0 | 1 | 2003 | Scalable Hardware-Based Multicast Trees · SC 2003 |
Interconnection networks and networks-on-chip
routing and switching |
0.0 | 1 | 2003 | Scalable Hardware-Based Multicast Trees · SC 2003 |
Interconnection networks and networks-on-chip › high-speed networks
supercomputer interconnect |
0.0 | 1 | 2009 | Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1formal verification · 0.1greedy algorithm · 0.0backtracking · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Efficient and Scalable Hardware-Based Multicast in Fat-Tree NetworksabstractThis article presents an efficient and scalable mechanism to overcome the limitations of collective communication in switched interconnection networks in the presence of faults. Considering that current trends in supercomputing are moving toward massively parallel computers, with many thousands of components, reliability becomes a challenge. In such scenario, fat-tree networks that provide hardware support for collective communication suffer from serious performance degradation due to the presence of, even, a single faulty node. This paper describes a new mechanism to provide high-performance collective communication in such situations. The feasibility of the proposed technique is formally demonstrated. We present the design of a new hardware-based routing algorithm for multicast, that is at the base of our proposal. The proposed mechanism is implemented and experimentally evaluated. Our experimental results show that hardware-based multicast trees provide an efficient and scalable solution for collective communication in fat-tree networks, significantly outperforming traditional solutions. Salvador Coll, Francisco J. Mora, José Duato, Fabrizio Petrini |
IEEE Trans. Parallel Distributed Syst. | 2 |
| 2003 | Scalable Hardware-Based Multicast TreesabstractThis paper presents an algorithm for implementing optimal hardware-based multicast trees, on networks that provide hardware support for collective communication. Although the proposed methodology can be generalized to a wide class of networks, we apply our methodology to the Quadrics network, a state-of-the-art network that provides hardware-based multicast communication. The proposed mechanism is intended to improve the performance of the collective communication patterns on the network, in those cases where the hardware support can not be directly used, for instance, due to some faulty nodes. This scheme provides significant reduction on multicast latencies compared to the original system primitives, which use multicast trees based on unicast communication. A backtracking algorithm to find the optimal solution to the problem is presented. In addition, a greedy algorithm is presented and shown to provide near optimal solutions. Finally, our experimental results show the good performance and scalability of the proposed multicast tree in comparison to the traditional unicast-based multicast trees. Our multicast mechanism doubles barrier synchronization and broadcasts performance when compared to the production-level MPI library. Salvador Coll, José Duato, Fabrizio Petrini, Francisco J. Mora |
SC | 4 |
| 2001 | A First Implementation of In-Transit Buffers on Myrinet GM SoftwareabstractClusters of workstations (COWs) are becoming increasingly popular as a cost-effective alternative to parallel computers. In these systems, the interconnection network connects hosts using irregular topologies, providing the wiring flexibility, scalability, and incremental expansion capability required in this environment. Myrinet is the most popular network used to build COWs. It uses source routing with the up*/down * routing algorithm. In previous papers we proposed the In-Transit Buffer (ITB) mechanism that improves network performance by allowing minimal routing, balancing network traffic, and reducing network contention. The mechanism is based on ejecting packets at some intermediate hosts and later re-injecting them into the network. Moreover, the ITB mechanism does not require additional hardware as it can be implemented on the software running at Myrinet network adapters. In this paper, we present a first implementation of the ITB mechanism on Myrinet GM software. We show the changes required in packet format and the modifications performed in the Myrinet Control Program (MCP). In addition, both the overhead introduced by the new code and the cost of extracting and re-injecting packets are measured. Results show that, even for this simple implementation, code overhead is only about 125 ns per packet and the message latency increase for messages that use the ITB mechanism is around 1.3 s per ITB. This is the first attempt to implement this mechanism, showing that a real implementation of ITBs is feasible on Myrinet COWs, and the associated overhead does not restrict the potential benefits of this mechanism. 1. Salvador Coll, José Flich, Manuel P. Malumbres, Pedro López 0001, José Duato, Francisco J. Mora |
IPDPS | 6 |
| 2001 | Cryptography Regulations for E-commerce and Digital Rights Management
Andres Torrubia, Francisco J. Mora, Luis Marti |
Comput. Secur. | 2 |
| 2000 | Information Security in Multiprocessor Systems Based on the X86 Architecture
Andres Torrubia, Francisco J. Mora |
Comput. Secur. | 2 |