This paper presents a unified view of a number of dimension reduction techniques under the common framework of tensors. Specifically, it is established that PCA, and the recently introduced 2-D PCA and Generalized Low Rank Approximation of Matrices (GLRAM), are special instances of the higher order orthogonal iteration of tensors (HOOI). The connection of these algorithms to HOOI has not been pointed out before in the literature. The pros and cons of these specializations versus HOOI are discussed.

In this paper, we develop from various points of view the TIme-Constant Equilibration Reduction (TICER) algorithm, a circuit-reduction method that converts a given$RC$network into a smaller$RC$network (one with fewer nodes and branches) by eliminating nodes that have few neighbors and small nodal time constants. Advantages of TICER include: great efficiency, intuitive error control, preservation of sparsity, output in the form of an$RC$network, and the ability to handle networks with many ports.

To extrapolate from one point to another using a line, one had better get the slope right. In this paper we apply a similar concept to the important problem in Static Timing Analysis (STA) of predicting cell timing for RC loads using capacitive characterization data. Instead of a line we have a Thevenin circuit, and instead of matching slopes we match load sensitivities. We present a table driven, highly accurate cell delay and slew prediction procedure that can improve STA when interconnect effects dominate. It is significantly more accurate (especially slew) than previously published Ceff methods.

Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed using the concept of an effective capacitance, C/sub eff/. Most published algorithms for C/sub eff/, however, require special cell characterization or supplemental information that is not part of standard timing libraries. In this paper we present a novel C/sub eff/ algorithm that is strictly compatible with existing timing libraries. It is also fast, easily implemented, and quite accurate-within 3% of transistor-level simulation in our tests. The method is based on approximating a gate by a current source, estimating the delay difference when the gate drives the actual RC load and a reference capacitor, and then converting the delay discrepancy into a C/sub eff/ value. Central to carrying out this program is the innovative concept of delay correction transfer function.

This paper develops the noise-counterparts to familiar delay formulas like Elmore or PRIMO. By matching the first few moments of the network's transfer impedance, we obtain efficient and accurate predictions for maximum noise between two capacitively coupled RC networks. Unlike many crosstalk equations in the literature, the method applies to general topologies and models transition-time dependence as well. Efficient enough for large circuits, the moment-matching noise formulas developed here can serve as a key ingredient in CAD methodologies that ensure a layout is free of noise problems.

A novel method which can be regarded as the noise-counterpart of the celebrated Elmore's delay formula-both being based on the first two moments of the network's transfer function-efficiently and accurately predicts maximum noise between two capacitively coupled RC networks, without simulation. The method applies to general topologies (with significant simplification for coupled trees), accurately models how coupling varies with driver transition time, and quantifies the uncertainty in the calculated noise values. Efficient enough for large circuits, the new method can serve as a key ingredient in CAD methodologies to ensure that a layout is noise-problem free.

Article Free Access Share on ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization Author: Bernard N. Sheehan Mentor Graphics, Wilsonville, OR Mentor Graphics, Wilsonville, ORView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 17–21https://doi.org/10.1145/309847.309855Published:01 June 1999Publication History 75citation449DownloadsMetricsTotal Citations75Total Downloads449Last 12 Months32Last 6 weeks6 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Projective convolution (PC) is a provably passive and numerically well-conditioned model-order reduction technique for large RLC circuits including those with floating capacitors or inductor loops. Unlike moment-matching which operates in the frequency domain, PC is positioned squarely in the time domain: it matches the impulse response of a circuit by projecting with the Krylov space formed by solving the discretized differential equations of the circuit. PC gives excellent results for coupled lines, large RLC meshes, and clock trees.

Time Constant Equilibration Reduction (TICER) is a novel RC reduction method tailored for extract/reduce CAD tools. Geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. The resulting RC circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, TICER produces smaller, less-stiff RC networks. It produces realizable RC circuits; can retain original network topology; scales well to large networks (/spl sim/10/sup 7/ nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.

We present a technique for rapidly calculating printed circuit board (PCB) interconnect delays.Because of ringing, plateaux, and other signal integrity effects, delay estimation with low order macromodels is more difficult for PCB nets than for VLSI interconnect.A moment matching method for interconnect trees is described in which moments are computed by a tree traversal algorithm using ABCD matrices.Moment contributions from distributed transmission lines are calculated directly.This is a simplification compared to methods which must first approximate the line as a lumped RLC ladder; it also makes time of flight extraction trivial.Order descent is used to ensure stability.When applied to a real PCB design, the method was accurate and impressively fast--588 nets, or 4496 delays, in 12 seconds on a PC!