In-memory computing aims to bring forward application data from the storage to the server's main memory. By locating the working set closer to its application, in memory, great performance gains can be achieved. Most approaches in this arena have built solutions that either need traditional applications to be re-written or require new software acquisition.

In this paper, fundamental conditions which bound the network processing unit (NPU) worst-case performance are established. In particular, these conditions formalize and integrate, with mathematical rigor, two existing approaches for finding the NPU performance bounds, i.e., the work conserving condition and instruction/latency budget based approaches. These fundamental conditions are then employed to derive tight memory access latency bounds for a data path flow with one memory access. Finally, one of these memory access latency bounds is successfully used to interpret a peculiar phenomenon found in Intel IXP1200, demonstrating the importance of analytical modeling for NPU performance analysis.