This work presents a novel Single Capacitively Coupled (SCC) ring Voltage-Controlled Oscillator (VCO) designed for wideband N-path systems. It reduces the number of capacitors by half compared to the Double Capacitively Coupled (DCC) design, potentially requiring less silicon area while maintaining improved phase noise performance compared to the pseudo differential ring VCO, and with less power consumption than the DCC design. The proposed SCC VCO, tunable from 0.3 to 3.0 GHz, achieves the lowest power consumption among the state-of-the-art designs compared, consuming just 0.48 mW at 3 GHz, with a phase noise of -76.5 dBc/Hz at 1 MHz offset. Consequently, the figure of merit (FOM) remains modest at -147 dBc/Hz, comparable to other designs but leaving room for improvement. The analysis reveals that improper configuration may lead to unwanted oscillation modes of the three VCOs analyzed, making a startup circuit essential for stable operation. These results position the SCC ring VCO as a promising candidate for low-power, high-performance applications.

This paper presents a programmable current source circuit aimed at neuromodulation applications capable of achieving a peak efficiency of 98 % during the stimulation phase. It also offers a high voltage compliance almost 10 V. The circuit is based on our previous work that leverages a small drain-source voltage of transistors working in the triode region to improve the efficiency. The circuit was designed in a commercially-available 180 nm HV CMOS technology. The circuit area is 0.021 mm2. The circuit achieves a minimum operating output voltage of just 17 mV.

Design methods for MOS analog circuits that derive from the gm/ID methodology have extended the idea of using the ratio of key design parameters. In this way a general characteristic for the transistors of a given length in a given process is obtained. This paper provides a brief overview of these analog design approaches that can be called ratio based, contributing to show a general vision about them. Then, it is shown, based on analytical derivations, simulations and measure-ments, how the ratio based analog approach can be extended to include the second and third derivative of the current and the distortion terms related to them. The proposed approach provides characteristics that hold for all transistors of a given length (letting aside narrow channel effects in very narrow transistors) and provide a tool to guide the design process in aspects related to distortion assessment.

Lately efforts have been made to have compact models for nanoscale processes with a small number of parameters. These models consider one to four extra parameters in addition to the three basic parameters of the long-channel transistor compact models, which are the slope factor, the equilibrium threshold voltage and the normalization current. An acceptable accuracy of the dc characteristics and the small-signal parameters is obtained through these models. This work analyzes whether it is possible to obtain an adequate model of the intrinsic part of the capacitances by means of these models and parameters, while proposing a simple method to account for the extrinsic part of the capacitances. The proposed method, together with the model, is tested for minimum-length transistors in an FD-SOI 28 nm process and applied to the design of a low-voltage LC oscillator. The results obtained by these means are compared with the results of a look-up table approach and with simulation results, showing a reasonable agreement.

The Latin American Symposium on Circuits and Systems (LASCAS) is the flagship conference in Latin America (IEEE Regions 9) by the IEEE Circuits and Systems Society (CASS). This conference contributes since more than a decade to its history by reporting the latest research results and innovations across the themes within the scope of the society, including analog, digital, and mixed-signal electronics, signal processing, power electronics, communication theory, sensors, circuit theory, and nonlinear circuits and systems.

The Swedish Institute of Computer Science Parasitic Interference Directional Antenna (SPIDA) is an electrically switched directional antenna that uses switched beamforming techniques to shape the antenna radiation pattern focusing the transmitted power in a given direction, increasing the maximum gain, and simultaneously reducing interference in other directions. This work extends the use of the SPIDA antenna, showing that using multiple director elements results in an improved performance in terms of maximum gain, narrower Half Power Beamwidth (HPBW), and a lower module of the S11 parameter. Measurements show that using three directors improves the maximum gain about 1.4 dB (6.8 dBi for the single director element antenna against 8.2 dBi for the antenna with three directors); the input impedance matching was also improved, obtaining a module of S11 parameter of -9.8 dB at the central frequency ( fc = 2.4525 GHz) against -7.5 dB for the antenna with a single director element. Finally, new intermediate directions of transmission can be achieved by using two successive director elements, where the power is focused in the bisectrix of the angle formed by the two directors. This converts a six-sector antenna like the SPIDA into a twelve-sector antenna without changing the hardware.

This paper presents a simple but still powerful approach for the analysis of the average power consumption of a sensor node using the IPv6 over Low power and Lossy Networks (LLN) stack, which is one of the most widely adopted and promising communication stacks. Power consumption is broken down according to the node states (i.e. CPU, IRQ, LPM, Tx, Rx) and according to the network protocols (e.g. CoAP, RPL, 6LoWPAN, Contiki MAC), identifying the relative weight of each protocol in the total energy consumption for several configurations. Results show that the Low Power Listening (LPL) mechanism of the radio duty cycling layer and RPL control messages have the highest impact on the total energy consumption, while the application's report rate has a very low impact for periods over 60 seconds.

The ultimate goal of the movie industry is to create an emotion from a story. However it is difficult to measure this emotional impact on an user. Questionnaires or other audience measurement techniques are often used, but with well known biases difficult to remove. We propose here an objective solution based on the viewer's physiological response (aka the EDA or GSR signals). The demonstration consists of an on the fly and live capture of an user's physiological signals, corresponding to his unconscious body reaction, and the real-time computing and display of the corresponding user's "affective profile".

The ever-increasing complexity of applications covered by wireless sensor networks (WSNs) demands for increasing memory size, which in turn increases the power drain. It is well known that SRAM power consumption can be reduced by employing a banked structure, where unused banks are switched into the low leakage retention mode. In this work, we propose a new strategy for memory banking, taking advantage of the software properties of WSN, and achieving aggressive power savings. We present a detailed model for the energy saving for equally sized banks with two power management schemes: a best-oracle policy and a simple greedy policy. Thanks to our modeling, at design time the optimum number of banks can be estimated, and the design can reach huge energy savings. The memory content allocation and the power management problem were solved by an integer linear program formulation for two real wireless sensor network application (based on TinyOS and ContikiOS). Experimental results show an energy reduction of up to 77.4% for a partition overhead of 1%.

The ability to assess fine-scale user responses has applications in advertising, content creation, recommendation, and psychology research. Unfortunately, current approaches, such as focus groups and audience surveys, are limited in size and scope. In this paper, we propose a combined biometric sensing and analysis methodology to leverage audience-scale electro-dermal activity (EDA) data for the purpose of evaluating user responses to video. We provide detailed characterization of how temporal physiological responses to video stimulus can be modeled, along with first-of-its-kind audience-scale EDA group experiments in uncontrolled real-world environments. Our study provides insights into the techniques used to analyze EDA, the effectiveness of the different temporal features, and group dynamics of audiences. Our experiments demonstrate the ability to classify movie ratings with accuracy of over 70% on specific films. Results of this study suggest the ability to assess emotional reactions of groups using minimally invasive sensing modalities in uncontrolled environments.

This work presents an architecture of neural recording amplifier based on a modified differential difference amplifier (DDA). The proposed circuit improves the performance with respect to capacitive feedback neural amplifiers and standard DDA based amplifiers by taking advantage of the high CMRR achievable in a DDA without jeopardizing the power consumption. In addition a novel technique for rejecting the DC component at the output of the amplifier and fixing the low cut-off frequency is described. The expected performance of the circuit is checked by Monte Carlo simulation, achieving 48dB gain in a 250Hz-8kHz bandwidth, with higher than 107dB CMRR (@5kHZ), 2.4μVrms input noise and 4.2 noise efficiency factor at a total current consumption of 16.5μA from a 3.3V power supply in a 0.5μm CMOS technology.

Traffic anomaly detection has received a lot of attention over recent years, but understanding the nature of these anomalies and identifying the flows involved is still a manual task, in most cases. We introduce Unsupervised Root Cause Analysis (URCA) which isolates anomalous traffic and classifies alarms with minimal manual assistance and high accuracy. URCA proceeds by successive reduction of the anomalous space, eliminating normal traffic based on feedback from the anomaly detection method. Classification is done by clustering a new anomaly with previously labeled events. We validate URCA using manually analyzed real anomalies as well as synthetic anomaly injection. Our validation shows that URCA can accurately diagnose a large range of anomaly types, including network scans, DDoS attacks, and major routing changes.

In this work a design flow for class C radiofrequency (RF) power amplifiers (PA) with on-chip output networks in nanometric technologies is presented. This is a new parasitic-aware method intended to reduce time-consuming iterations which are normally required in fully-integrated designs. Unlike other methods it is based on actual transistors DC characteristics and inductors data both extracted by simulation. Starting from the output power specifications a design space map is generated showing the trade-offs between efficiency and components sizing, thus enabling the selection of the most appropriate design that satisfies the harmonic distortion requirements. As a proof of concept of the proposed method, a design example for an IEEE 802.15.4 2.4 GHz PA in a 90 nm CMOS technology is presented.

When many flows are multiplexed on a non-saturated link, their volume changes over short timescales tend to cancel each other out, making the average change across flows close to zero. This equilibrium property holds if the flows are nearly independent, and it is violated by traffic changes caused by several, potentially small, correlated flows. Many traffic anomalies (both malicious and benign) fit this description. Based on this observation, we exploit equilibrium to design a computationally simple detection method for correlated anomalous flows. We compare our new method to two well known techniques on three network links. We manually classify the anomalies detected by the three methods, and discover that our method uncovers a different class of anomalies than previous techniques do.

When many flows are multiplexed on a non-saturated link, their volume changes over short timescales tend to cancel each other out, making the average change across flows close to zero. This equilibrium property holds if the flows are nearly independent, and it is violated by traffic changes caused by several correlated flows. We exploit this empirical property to design a computationally simple anomaly detection method.

Traffic anomalies are specific types of events and conditions which differ from the normal or expected network behavior, and therefore should be brought to the attention of network operators. Examples of such events include, but are not limited to link or router outages, Denial-of-Service (DoS) attacks, flash crowds, port scans and misconfigured devices.

Multiple network-wide anomaly detection techniques proposed in the literature define an anomaly as a statistical outlier in aggregated network traffic. The most popular way to aggregate the traffic is as a Traffic Matrix, where the traffic is divided according to its ingress and egress points in the network. However, the reasons for choosing traffic matrices instead of any other formalism have not been studied yet. In this paper we compare three network-driven traffic aggregation formalisms: ingress routers, input links and origin-destination pairs (i.e. traffic matrices). Each formalism is computed on data collected from two research backbones. Then, a network-wide anomaly detection method is applied to each formalism. All anomalies are manually labeled, as a true or false positive. Our results show that the traffic aggregation level has asignificant impact on the number of anomalies detected and on the false positive rate. We show that aggregating by OD pairs is indeed the most appropriate choice for the data sets and the detection method we consider. We correlate our observations with time series statistics in order to explain how aggregation impacts anomaly detection.

A tool that explores the design space of basic RF circuit blocks is presented. The tool takes advantage of the application of an MOS transistor model continuous in all inversion levels (weak to strong inversion). The performance of the circuit is analyzed in the ID-gm/IDplane. The tool shows the existence of an inversion level that provides an optimum in the power consumption for a given gain and frequency. Examples are presented showing how comparison of the performance of different technologies or evaluation of the effect of parasitic elements can be easily done. The tool is applied to the design of a power amplifier and a VCO at 910 MHz in 0.35 mum CMOS technology. The tools estimations are checked against simulations using BSIM3v3, showing very good agreement. Additionally, preliminary experimental results are presented