Quality assessment is crucial to developments of video communication systems. While subjective test yields most accurate results, its expensive cost and human biasness make it an unsatisfactory figure of merit. The peak-signal to noise ratio (PSNR), the most acceptable objective video quality assessment metric, is based on error sensitivity; its failure to capture perceptual errors is well documented. Other perceptual quality metrics fail to detect the localized errors that are common in sequences produced by low bit-rate video communication systems. In this work, a novel perceptual quality assessment metric, the structural similarity (SSIM) metric, is modified to better detect spatial artifacts often seen in video communication systems

This paper presents an efficient method to reduce the implementation complexity of discrete wavelet transform (DWT) for JPEG 2000 standard. The proposed method is based on the design and the implementation of integer wavelets. Instead of using the lifting scheme or sacrificing vanishing moment to obtain integer coefficients, the proposed method derives integer coefficients directly from roots of the half band filter. Based on the integer filter coefficients, we propose an efficient VLSI algorithm, which uses only 17 integer adders and 15 shifters to construct a two-channel filter bank system. The complexity of the proposed method is significantly lower than that found in the convolution and lifting approaches. The convolution approach requires 9 floating-point multiplications and 14 floating-point additions. Likewise, the lifting scheme needs 6 floating-point multiplications and 12 floating-point additions. Besides the mathematical derivation, this paper presents simulation results, which compare the frequency responses and coding efficiency between the floating-point and the integer approaches. In addition, a VHDL implementation result is presented.

New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power savings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however, is not achieved easily: a design originally targeted for implementation in a 5 V technology will typically require significant rework to meet timing and throughput requirements at the lower operating voltage. In this paper we describe a high-level synthesis system which assists the designer in performing this task, minimizing the need for manual redesign. Techniques employed in this work include pipelining and a new approach to module selection that minimizes power consumption subject to timing constraints. Using these and other high-level synthesis techniques to target designs to 3.3 V libraries, we show that it is possible to reduce power consumption by as much as 56% as compared to the original 5 V implementation, while meeting specified minimum throughput and maximum latency constraints.

Real-world problems can often be couched in terms of conditional probability density function estimation. In particular, pattern recognition, signal detection, and financial prediction are among the multitude of applications requiring conditional density estimation. Previous developments in this direction have used neural nets to estimate statistics of the distribution or the marginal or joint distributions of the input-output variables. We have modified the joint distribution estimating sigmoidal neural network to estimate the conditional distribution. Thus, the probability density of the output conditioned on the inputs is estimated using a neural network. We have derived and implemented the learning laws to train the network. We show that this network has computational advantages over a brute force ratio of joint and marginal distributions. We also compare its performance to a kernel conditional density estimator in a larger scale (higher dimensional) problem simulating more realistic conditions.

No abstract available.

Blind signal separation (BSS) is a powerful technique for separation of mixed signals with weak assumptions on the incoming signals. The objectives of BSS are analogous to the objectives of exploratory projection pursuit which is widely used in the statistical community for finding structure in high dimensional data sets. In this paper, we adapt exploratory projection pursuit for BSS. First, we introduce exploratory projection pursuit and the associated projection pursuit index (PPI). We adapt the PPI for application to BSS. We also investigate the order of approximation required to achieve satisfactory separation using the PPI, and compare its performance to a maximum-likelihood BSS technique using a Gram-Charlier expansion.

This paper presents a new wire length estimation technique for row-based design. Noting that the local topological structure of the network is often reflected in the local structure of the placement, we present a technique of topological analysis of the network, in which the local structure of the network is characterized by a growing sequence of multilevel neighborhoods. By assuming a pointwise independent branching process, we derive equations for the probability density of multilevel neighborhoods. The wire length distribution is found by solving these equations. For thirteen industrial circuits tested, this technique gives an average of 15.1% estimation accuracy.

The scalable coherent interface (SCI) is a newly established IEEE standard that provides bus-like services to a network of nodes without actually using a physical bus. Rather, it utilizes very fast, unidirectional links that can be arranged into a variety of topologies. SCI provides a novel fairness protocol that equally allocates bandwidth to all nodes on the network. When global fairness is not required, it is often desirable to relax its enforcement, in exchange for increased network utilization and better load balancing. This paper presents an extension to the SCI flow control protocol that increases network utilization and, hence, attainable system throughput by enforcing fairness only among nodes whose transmissions interfere with one another. The enhanced protocol grants a node as much bandwidth as it requires, as long as its transmissions do not inhibit those of other nodes. Although this is commonly known as max-min fairness, we more descriptively refer to it as relaxed fairness. We present extensive simulation results and compare them to the standard SCI protocol and to our desired performance, which has been preciously derived in the literature. The comparisons show that, on average, this enhancement can provide a substantial increase in performance over the original protocol.

A radial basis function neural network was successfully applied to an area which is relatively new for neural networks: a remote sensing application that provides estimates of water vapor content, an important parameter for climate modeling. The neural network provided results which are up to 32% better than had been previously obtained using conventional statistical methods on the same data. These results have implications for improved short-term weather forecasting and for long-term global climate modeling. The neural network approach is compared with the past and present operating algorithms at the National Oceanic and Atmospheric Administration. The radial basis function network's performance is compared with sigmoidal backpropagation network. Low-power electronic implementations of the neural methodology were explored to demonstrate the feasibility of placing the network on a remote sensing platform. This would permit processing the raw sensor data into information on the platform, eliminating the need to store the raw data, and helping to contain the expected explosion of climate data.

A supervised learning neural network (SLNN) coprocessor which enhances the performance of a digital soft-decision Viterbi decoder used for forward error correction in a digital communication channel with either fading plus additive white Gaussian noise (AWGN) or pure AWGN has been investigated and designed. The SLNN is designed to cooperate with a phase shift keying (PSK) demodulator, an automatic gain control (AGC) circuit, and a 3-bit quantizer which is an analog to digital convertor. It is trained to learn the best uniform quantization step-size Delta (BEST) as a function of the mean and the standard deviation of various sets of Gaussian distributed random variables. The channel cutoff rate (R(0)) of the channel is employed to determine the best quantization threshold step-size (Delta(BEST)) that results in the minimization of the Viterbi decoder output bit error rate (BER). For a digital communication system with a SLNN coprocessor, consistent and substantial BER performance improvements are observed. The performance improvement ranges from a minimum of 9% to a maximum of 25% for a pure AWGN channel and from a minimum of 25% to a maximum of 70% for a fading channel. This neural network coprocessor approach can be generalized and applied to any digital signal processing system to decrease the performance losses associated with quantization and/or signal instability.

This paper outlines the development of a rapid prototype methodology used to implement a new communications decoding architecture and a channel simulator to evaluate that decoder's performance. In addition, we describe the subsequent refinement of a key computational component of the decoder using a semicustom approach; namely, a CMOS standard cell implementation. Both these project tasks have relied extensively on the use of design automation (DA) tools and Field Programmable Gate Array (FPGA) technology. Herein, we describe our rapid prototype methodology, some lessons learned, and highlight our experiences using DA tools (specifically, Mentor Graphics and Xilinx) encountered in the progress of our work.

New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power servings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however is not achieved easily: a design originally targeted for implementation in a 5 V technology will typically require significant re-work to meet timing and throughput requirements at the lower operating voltage. We describe a high-level synthesis system which assists the designer in performing this task, minimizing the need for manual re-design. Techniques employed in this work include pipelining and a new approach to module selection which minimizes power consumption subject to timing constraints. Using these and other high-level synthesis techniques to target designs to 3.3 V libraries, we show that it is possible to reduce power consumption by as much as 56% as compared to the original 5 V implementation, while meeting specified minimum throughput and maximum latency constraints.>

An approach toward ath-oriented tirnii -driven place-{ t ment is proposed.We rst transform the p acement with timing constraints to a Lagrange problem, A primal-dual a.ppro~IS USed to find the optimrd relative module locatlons.In each primal dual iteration, the primal problem is solved by a piecewise linear resistive network method, whale the dual process is used to update the Lagrange multiplier.The sparsity of the piecewiee liiear resistive network is exploited to obt airt dramatic improvement on the efficiency of the calculation.Up to 22.o% of clock cycle reduction was observed for Primary2 test case.1

The scalable coherent interface (SCI) is a newly established IEEE standard which provides bus-like services to a network of nodes connected by very fast, unidirectional links. SCI provides an efficient flow control protocol that fairly allocates bandwidth to all nodes on the network. When global fairness is not required, it is desirable to relax its enforcement, in exchange for increased network utilization. This paper presents an extension to SCI's fairness protocol that increases attainable throughput by enforcing fairness only among conflicting nodes. The authors present extensive simulation results and compare them to the standard SCI protocol and to the desired performance, which is derived in the paper. The comparisons show that, on average, the enhancements substantially increase the performance of the original protocol.>

High performance multiprocessing systems have been increasingly using heterogeneous digital signal processors (DSPs) for overall systems gain. Scheduling a DSP algorithm on such a system must address issues of interprocessor communication as well as parallelism extraction for optimal throughput. These issues have been extensively examined for multiprocessor systems incorporating homogeneous processors. A heterogeneous macropipelined scheduling scheme has been described which addresses the aforementioned communication and parallelization issues. The advantage of resorting to a heterogeneous scheme in specific cases is illustrated with examples.>

It is well known that the computational workload of finite impulse response (FIR) filters can be significantly reduced using the prefilter-equalizer approach. A technique for rounding the tap coefficients of the equalizer to a single power-of-two (or a small combination of powers-of-two) with little or no degradation in overall filter performance is described. Using error spectrum shaping, the equalizer coefficient truncation error is moved to higher frequencies where it is attenuated by the prefilter. The resulting equalizer requires no multiplications and is typically only of slightly higher order than an optimal direct form equalizer with infinite precision coefficients. Examples are given showing a 4*decrease in arithmetic complexity over previous prefilter-equalizer approaches and a 1.5*decrease over optimal interpolated FIR approaches.>

KINFIDA (knowledge-based intelligent filter design assistant), a hybrid knowledge-based system with a model-based reasoning architecture for digital filter design, is described. It extends the concept of an isolated digital signal processing CAD tool and provides a closed-loop design environment where the system expertise can grow incrementally with minimal effect on the controls and the reasoning process. It utilizes IEEE signal processing libraries and is implemented in Nexpert Object, a commercial object-rule-based development system. The user interface is implemented using the X11 toolkit package. Using an interactive human interface, KINFIDA suggests likely filter approaches, estimates undetermined parameters, provides performance estimates, and suggests candidate VLSI technologies satisfying a desired filtering operation.>

A neural network decoder designed to provide a constant output of decoded data for long-constraint-length convolutional codes (K⩾11) is presented. With only local connections between neurons and digital EX-OR cells, direct hardware implementation in a VLSI ASIC (application-specific integrated circuit) is feasible. Decoder strategy is discussed along with toggling strategy. Architectural modifications to decode other code rates are also discussed

This paper presents the extension of bit-serial architectures for next-generation signal processing chips with floating-point and fault-tolerant capabilities. The architecture and design of a novel bit-serial floating-point complex multiplier-accumulator (CMAC) hardware is described. Fault-tolerant features are incorporated by embedding these CMACs into dynamically reconfigurable systolic arrays. The arrays can be utilized for FIR filtering, convolution, correlation and other signal processing applications based upon multiply-accumulate. Furthermore, these computational cores can be incorporated into more complex processors which perform FFT-type computations. With the advent of submicron VLSI technology, the smaller device geometries will afford either the implementation of greater functionality and/or computational capabilities. These increased capabilities will enable the solution of more demanding signal processing problems where there exist broad dynamic range requirements or low signal to noise conditions. But also associated with the increased functionality is the greater need for fault tolerance in high performance applications. Our bit-serial floating-point complex multiplier-accumulator will serve many such signal processing needs.

The Cornell University Signal Processor (CUSP) is a high performance CMOS processor which has been custom designed in VLSI to efficiently compute digital signal processing algorithms based on the Cooley-Tukey Radix-4 Fast Fourier Transform. One CUSP chip can be used as a stand-alone peripheral in a microprocessor system, or CUSP units can be combined into arrays in order to process signals with sampling rates of several MHz. It can attain a high numerical accuracy while maintaining a throughput superior to most available systems. In this paper we discuss the signal processing capabilities of CUSP, its simple programmability, and I/O interface. We also present simulation results which quantify the signal-to-noise ratio advantages of the bit-serial architecture.