Scaling quantum computers from a few qubits to large numbers remains one of the critical challenges in realizing practical quantum advantage. Multi-core quantum architectures have emerged as a promising solution, enabling scalability through distributed quantum processing units (QPUs) interconnected via classical and quantum links. However, the bottleneck of wired connections persists, as densely packed wired interconnects, both vertically across temperature stages and horizontally within the same layer, introduce spatial constraints, power dissipation, and latency, which could hinder performance as the number of QPUs increases. To overcome these limitations, this work proposes a cryo-compatible on-chip differential dipole antenna operating at 28 GHz to enable short-range wireless communication within a quantum computer cryostat. Temperature-dependent material properties are incorporated to accurately capture antenna behavior at 4 K. Moreover, by embedding the antenna in a realistic cryostat structure, we evaluate the feasibility of antenna operation within the cryogenic environment. The proposed antenna achieves a reflection coefficient of -20.8 dB in free space and -18.38 dB within the cryostat, demonstrating efficient impedance matching.

This work presents a routing-aware pruning strategy for quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) devices. We propose a method to remove parametric controlled rotations whose small rotation angles do not justify the routing overhead required for their implementation. By selectively pruning such gates, the method mitigates fidelity loss arising from additional SWAP operations introduced during compilation. Our approach evaluates whether executing a gate leads to greater fidelity loss than omitting it. Simulations on benchmark circuits with realistic noise models show that the method reduces two-qubit gate counts (up to 48.6%) while improving final state fidelity (up to 47.7%), especially for larger circuits where routing costs dominate.

Quantum technologies offer unprecedented capabilities in computation and secure information transfer. Their implementation requires qubits to operate at cryogenic temperatures (CT) while control and readout electronics typically still remains at room temperature (RT). As systems scale to millions of qubits, the electronics should also operate at CT to avoid a wiring bottleneck. However, wired power transfer from RT for such electronics introduces severe challenges, including thermal load between cooling stages, Joule heating, noise coupling, and wiring scalability. This paper addresses those challenges by evaluating several candidate architectures for scalable power transfer in the dilution frige: high-voltage (HV) wired power transfer, radiative wireless transfer, non-radiative wireless transfer, and a hybrid HV and non-radiative transfer. These architectures are analyzed in terms of thermal load, power loss, heating, coupling noise, power density, scalability, reliability, and complexity. Comparative analysis demonstrates the trade-offs among these architectures, while highlighting HV non-radiative transfer as a promising candidate for scalable quantum systems.

The scalability of quantum computing is constrained by the physical and architectural limitations of monolithic quantum processors. Modular multi-core quantum architectures, which interconnect multiple quantum cores (QCs) via classical and quantum-coherent links, offer a promising alternative to address these challenges. However, transitioning to a modular architecture introduces communication overhead, where classical communication plays a crucial role in executing quantum algorithms by transmitting measurement outcomes and synchronizing operations across QCs. Understanding the impact of classical communication on execution time is therefore essential for optimizing system performance. In this work, we introduce qcomm , an open-source simulator designed to evaluate the role of classical communication in modular quantum computing architectures. qcomm provides a high-level execution and timing model that captures the interplay between quantum gate execution, entanglement distribution, teleportation protocols, and classical communication latency. We conduct an extensive experimental analysis to quantify the impact of classical communication bandwidth, interconnect types, and quantum circuit mapping strategies on overall execution time. Furthermore, we assess classical communication overhead when executing real quantum benchmarks mapped onto a cryogenically-controlled multi-core quantum system. Our results show that, while classical communication is generally not the dominant contributor to execution time, its impact becomes increasingly relevant in optimized scenarios—such as improved quantum technology, large-scale interconnects, or communication-aware circuit mappings. These findings provide useful insights for the design of scalable modular quantum architectures and highlight the importance of evaluating classical communication as a performance-limiting factor in future systems.

In this work, we explore and propose several quantum circuit mapping strategies to optimize qubit shuttling in scalable quantum computing architectures based on silicon spin qubits. Our goal is to minimize phase errors introduced during shuttling operations while reducing the overall execution time of quantum circuits. We propose and evaluate five mapping algorithms using benchmarks from quantum algorithms. The Swap Return strategy emerged as the most robust solution, offering a superior balance between execution time and error minimization by considering future qubit interactions. Additionally, we assess the importance of initial qubit placement, demonstrating that an informed placement strategy can significantly enhance the performance of dynamic mapping approaches.

Waveguides potentially offer an effective medium for interconnecting quantum processors within a modular framework, facilitating the coherent quantum state transfer between the qubits across separate chips. In this work, we analyze a quantum communication scenario where two qubits are connected to a shared waveguide, whose resonance frequency may match or not match that of the qubits. Both configurations are simulated from the perspective of quantum electrodynamics (QED) to assess the system behavior and key factors that influence reliable interchip communication. The primary performance metrics analyzed are quantum state transfer fidelity and latency, considering the impact of key system parameters such as the qubit-waveguide detuning, coupling strength, waveguide decay rate, and qubit decay rate. We present the system design requirements that yield enhanced state transmission fidelity rates and lowered latency, and discuss the scalability of waveguide-mediated interconnects considering various configurations of the system.

Next-generation artificial intelligence (AI) workloads are posing challenges of scalability and robustness in terms of execution time due to their intrinsic evolving data-intensive characteristics. In this paper, we aim to analyse the potential bottlenecks caused due to data movement characteristics of AI workloads on scale-out accelerator architectures composed of multiple chiplets. Our methodology captures the unicast and multicast communication traffic of a set of AI workloads and assesses aspects such as the time spent in such communications and the amount of multicast messages as a function of the number of employed chiplets. Our studies reveal that some AI workloads are potentially vulnerable to the dominant effects of communication, especially multicast traffic, which can become a performance bottleneck and limit their scalability. Workload profiling insights suggest to architect a flexible interconnect solution at chiplet level in order to improve the performance, efficiency and scalability of next-generation AI accelerators.

Quantum computing represents a paradigm shift in computation, offering the potential to solve complex problems intractable for classical computers. Although current quantum processors already consist of a few hundred qubits, their scalability remains a significant challenge. Modular quantum computing architectures have emerged as a promising approach to scale up quantum computing systems. This article delves into the critical aspects of distributed multi-core quantum computing, focusing on quantum circuit mapping, a fundamental task to successfully execute quantum algorithms across cores while minimizing inter-core communications. We derive the theoretical bounds on the number of non-local communications needed for random quantum circuits and introduce the Hungarian Qubit Assignment (HQA) algorithm, a multi-core mapping algorithm designed to optimize qubit assignments to cores with the aim of reducing inter-core communications. Our exhaustive evaluation of HQA against state-of-the-art circuit mapping algorithms for modular architectures reveals a 4.9× and 1.6× improvement in terms of execution time and non-local communications, respectively, compared to the best-performing algorithm. HQA emerges as a very promising scalable approach for mapping quantum circuits into multi-core architectures, positioning it as a valuable tool for harnessing the potential of quantum computing at scale.

Design, simulation, analysis and verification methodologies are crucial for developing electronic circuits and systems at large. Whereas long-standing EDA software is used in the semiconductor technology, there is no counterpart for quantum computing systems yet. Although the quantum computing community started utilizing and adapting some of the already existing EDA tools, for instance, to design quantum processors and control electronics for driving the qubits, or even to solve some quantum computing design tasks, they do not fully use the expertise gained over the last decades in the field of design automation. Current intermediate-scale quantum computers have been designed in an ‘adhoc’ manner with heterogeneous methods and tools. As we are entering the large-scale era, it is timely and key to further adopt EDA methodologies and software for quantum computing. In this paper, we provide an overview on how full-stack quantum computing systems are being implemented nowadays and discuss which the main challenges are for transitioning from this current scenario to a comprehensive framework encompassing full automated system-wide architecting, design, simulation, verification, and test.

Quantum computing holds immense potential for solving classically intractable problems by leveraging the unique properties of quantum mechanics. The scalability of quantum architectures remains a significant challenge. Multi-core quantum architectures are proposed to solve the scalability problem, arising a new set of challenges in hardware, communications and compilation, among others. One of these challenges is to adapt a quantum algorithm to fit within the different cores of the quantum computer. This paper presents a novel approach for circuit partitioning using Deep Reinforcement Learning, contributing to the advancement of both quantum computing and graph partitioning. This work is the first step in integrating Deep Reinforcement Learning techniques into Quantum Circuit Mapping, opening the door to a new paradigm of solutions to such problems.

Designing efficient quantum processor topologies is pivotal for advancing scalable quantum computing architectures. The communication overhead, a critical factor affecting the execution fidelity of quantum circuits, arises from inevitable qubit routing that brings interacting qubits into physical proximity by the means of serial SWAP gates to enable the direct two-qubit gate application. Characterizing the qubit movement across the processor is crucial for tailoring techniques for minimizing the SWAP gates. This work presents a comparative analysis of the resulting communication overhead among three processor topologies: star, heavy-hexagon lattice, and square lattice topologies, according to performance metrics of communication-to-computation ratio, mean qubit hotspotness, and temporal burstiness, showcasing that the square lattice layout is favourable for quantum computer architectures at a scale.

Traditional dynamic energy management methods optimize the energy usage in wireless sensor nodes adjusting their behavior to the operating conditions. However, this comes at the cost of losing the predictability in the operation of the sensor nodes. This loss of predictability is particularly problematic for the battery life, as it determines when the nodes need to be serviced. In this paper, we propose an energy and relevance-aware monitoring method, which leverages the principles of self-awareness to address this challenge. On one hand, the relevance-aware behavior optimizes how the monitoring efforts are allocated to maximize the monitoring accuracy; while on the other hand, the power-aware behavior adjusts the overall energy consumption of the node to achieve the target battery life. The proposed method is able to balance both behaviors so as to achieve the target battery life, at the same time is able to exploit variations in the collected data to maximize the monitoring accuracy. Furthermore, the proposed method coordinates two different adaptive schemes, a dynamic sampling period scheme, and a dual prediction scheme, to adjust the behavior of the sensor node. The evaluation results show that the proposed method consistently meets its battery lifetime goal, even when the operating conditions are artificially changed, and is able to improve the mean square error of the collected signal by up to 20% with respect to the same method with the relevance-aware behavior disabled, and of up to 16% with respect the same algorithm with just the adaptive sampling period or the dual prediction scheme enabled. Consequently showing the ability of the proposed method of making appropriate decisions to balance the competing interest of its two behaviors and coordinate the two adaptive schemes to improve their performance.

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to cope with limited inter-chiplet routing resources, which complicate the design of the data interconnect and the power delivery network. Emerging in-package wireless technology is a promising strategy to address these challenges, as it allows to implement flexible chiplet interconnects while freeing package resources for power supply connections. To assess the capabilities of such an approach and its impact from a full-system perspective, herein we present an exploration of the performance of in-package wireless communication, based on dedicated extensions to the gem5-X simulator. We consider different Medium Access Control (MAC) protocols, as well as applications with different runtime profiles, showcasing that current in-package wireless solutions are competitive with wired chiplet interconnects. Our results show how in-package wireless solutions can outperform wired alternatives when running artificial intelligence workloads, achieving up to a 2.64× speed-up when running deep neural networks (DNNs) on a chiplet-based system with 16 cores distributed in four clusters.

Wireless communications in the terahertz band have been recently proposed as complement to conventional wired interconnects within computing packages. Such environments are typically highly reverberant, hence showing long channel impulse responses and severely limiting the achievable rates. Fortunately, this communications scenario is static and can be pre-characterized, which opens the door to techniques such as time reversal. Time reversal acts a spatial matched filter and has a spatiotemporal focusing effect, which allows not only to increase the achievable symbol rates, but also to create multiple spatial channels. In this paper, the multi-user capability of time reversal is explored in the context of wireless communications in the terahertz band within a computing package. Full-wave simulations are carried out to validate the approach, whereas modulation streams are simulated to evaluate the error rate as a function of the transmitted power, symbol rate, and number of simultaneous transmissions.

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

This paper proposes the use of a tunable$LC$resonator to read an array of qubits in a multiplexed fashion, by making the dispersive shift of the targeted qubit dominant. Cavity and circuit electrodynamics (QED) theory is shown to support this idea. The tunable capacitor array, in parallel with a superconducting inductance, is designed to maximize the quality factor by frequency range product,$Q\cdot\Delta\omega$. This approach only requires one RF signal to measure multiple qubits, which can facilitate quantum computing scaling.

Wireless communications at the chip scale emerge as a interesting complement to traditional wire-based approaches thanks to their low latency, inherent broadcast nature, and capacity to bypass pin constraints. However, as current trends push towards massive and bandwidth-hungry processor architectures, there is a need for wireless chip-scale networks that exploit and share as many channels as possible. In this context, this work addresses the issue of channel sharing by exploring the design space of multi-channel Medium Access Control (MAC) protocols for chip-scale networks. Distinct channel assignment strategies for both random access and token passing are presented and evaluated under realistic traffic patterns. It is shown that, even with the improvements enabled by the multiple channels, both protocols maintain their intrinsic advantages and disadvantages.

Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use a modular or multi-core architecture, in which different quantum processors (cores) are connected via quantum and classical links. This new architectural design poses new challenges such as the expensive inter-core communication. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed critical discussion of the quantum circuit mapping problem for multi-core quantum computing architectures is provided. In addition, we further explore the performance of a mapping method, which is formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.

Programmable metasurfaces constitute an emerging paradigm, envisaged to become a key enabling technology for Reconfigurable Intelligent Surfaces (RIS) due to their powerful control over electromagnetic waves. The HyperSurface (HSF) paradigm takes one step further by embedding a network of customized integrated circuit (IC) controllers within the device with the aim of adding intelligence, connectivity, and autonomy. However, little is known about the traffic that the network needs to support as the target electromagnetic function or boundary conditions change. In this paper, the framework of a methodology is introduced to characterize the workload of programmable metasurfaces which is then used to analyze the beam steering HSFs. The workload characterization leads to many useful insights into traffic behavior, including the spatio-temporal load incurred and the HSF limitations in terms of fine-grained tracking of moving targets. It is observed that the traffic is inherently bursty with an uneven spatial distribution of load and that finer resolution comes at the cost of an increased but less bursty load. An indoor mobility model indicates reasonable signaling load on the deployed surfaces. Finally, a statistical analysis on the traffic patterns is performed, showing that the incoming traffic can be well represented by an ON-OFF model.

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hypervectors). Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) systems have been recently proved to be one of the most energy-efficient options, due to hypervector manipulations in the memory itself that reduces data movement. Although implementations of HDC on single IMC cores have been made, their parallelization is still unresolved due to the communication challenges that these novel architectures impose and that traditional Networks-on-Chip and Networks-in-Package were not designed for. To cope with this difficulty, we propose the use of wireless on-chip communication technology in unique ways. We are particularly interested in physically distributing a large number of IMC cores performing similarity search across a chip, and maintaining the classification accuracy when each of which is queried with a slightly different version of a bundled hypervector. To achieve it, we introduce a novel over-the-air computing that consists of defining different binary decision regions in the receivers so as to compute the logical majority operation (i.e., bundling, or superposition) required in HDC. It introduces moderate overheads of a single antenna and receiver per IMC core. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. It is demonstrated that the proposed approach allows to both bundle at least three hypervectors and scale similarity search to 64 IMC cores seamlessly, while incurring an average bit error ratio of 0.01 without any impact in the accuracy of a generic HDC-based classifier working with 512-bit vectors.

Graph Neural Networks (GNNs) have garnered a lot of recent interest because of their success in learning representations from graph-structured data across several critical applications in cloud and HPC. Owing to their unique compute and memory characteristics that come from an interplay between dense and sparse phases of computations, the emergence of recon-figurable dataflow (aka spatial) accelerators offers promise for acceleration by mapping optimized dataflows (i.e., computation order and parallelism) for both phases. The goal of this work is to characterize and understand the design-space of dataflow choices for running GNNs on spatial accelerators in order for mappers or design-space exploration tools to optimize the dataflow based on the workload. Specifically, we propose a taxonomy to describe all possible choices for mapping the dense and sparse phases of GNN inference, spatially and temporally over a spatial accelerator, capturing both the intra-phase dataflow and the inter-phase (pipelined) dataflow. Using this taxonomy, we do deep-dives into the cost and benefits of several dataflows and perform case studies on implications of hardware parameters for dataflows and value of flexibility to support pipelined execution.

Deep neural network (DNN) models continue to grow in size and complexity, demanding higher computational power to enable real-time inference. To efficiently deliver such computational demands, hardware accelerators are being developed and deployed across scales. This naturally requires an efficient scale-out mechanism for increasing compute density as required by the application. 2.5D integration over interposer has emerged as a promising solution, but as we show in this work, the limited interposer bandwidth and multiple hops in the Network-on-Package (NoP) can diminish the benefits of the approach. To cope with this challenge, we propose WIENNA, a wireless NoP-based 2.5D DNN accelerator. In WIENNA, the wireless NoP connects an array of DNN accelerator chiplets to the global buffer chiplet, providing high-bandwidth multicasting capabilities. Here, we also identify the dataflow style that most efficienty exploits the wireless NoP's high-bandwidth multicasting capability on each layer. With modest area and power overheads, WIENNA achieves 2.2X-5.1X higher throughput and 38.2% lower energy than an interposer-based NoP design.

In the quest of large-scale quantum computers, multi-core distributed architectures are considered a compelling alternative to be explored. A crucial aspect in such approach is the stringent demand on communication among cores when qubits need to interact, which conditions the scalability potential of these architectures. In this work, we address the question of how the cost of the communication among cores impacts on the viability of the quantum multi-core approach. Methodologically, we consider a design space in which architectural variables (number of cores, number of qubits per core), application variables for several quantum benchmarks (number of qubits, number of gates, percentage of two-qubit gates) and inter-core communication latency are swept along with the definition of a figure of merit. This approach yields both a qualitative understanding of trends in the design space and companion dimensioning guidelines for the architecture, including optimal points, as well as quantitative answers to the question of beyond which communication performance levels the multi-core architecture pays off. Our results allow to determine the thresholds for inter-core communication latency in order for multi-core architectures to outperform single-core quantum processors.

In the midst of the NISQ era of quantum computers, the challenges are gravitating to encompass both architecting and full-stack engineering aspects, which are inherently algorithm-driven, so that there starts to be a convergence of bottom-up and top down design approaches, what we coin as the Quantum Architecting (QuArch) era. In face of many-fold diverse design proposals, in this paper it is postulated and proposed to apply the so-called Design Space Exploration (DSE) to the full vertical stack of quantum systems as an instrumental methodology to address such design diversity challenge. This structured design means, based upon composing a multidimensional input design space together with compressing the set of output performance metrics into an optimization-oriented overall figure of merit, provides a framework and method for optimization, for performance comparison. It yields as well a way to discriminate among alternative techniques at all layers and across layers, eventually as a structured and comprehensive design-oriented formal framework to address the quantum system design and evaluation complexity. The paper concludes by illustrating instances of this methodology in optimizing and comparing mapping techniques to address the resource-constrained current NISQ quantum chips, and to carry out a quantitative gap analysis of scalability trends aiming manycore distributed quantum architectures.

Relational data present in real world graph representations demands for tools capable to study it accurately. In this regard Graph Neural Network (GNN) is a powerful tool, wherein various models for it have also been developed over the past decade. Recently, there has been a significant push towards creating accelerators that speed up the inference and training process of GNNs. These accelerators, however, do not delve into the impact of their dataflows on the overall data movement and, hence, on the communication requirements. In this paper, we formulate analytical models that capture the amount of data movement in the most recent GNN accelerator frameworks. Specifically, the proposed models capture the dataflows and hardware setup of these accelerator designs and expose their scalability characteristics for a set of hardware, GNN model and input graph parameters. Additionally, the proposed approach provides means for the comparative analysis of the vastly different GNN accelerators.

Recent developments in nanotechnology herald nanometer-sized devices expected to bring light to a number of groundbreaking applications. Communication with and among nanodevices will be needed for unlocking the full potential of such applications. As the traditional communication approaches cannot be directly applied in nanocommunication, several alternative paradigms have emerged. Among them, electromagnetic nanocommunication in the terahertz (THz) frequency band is particularly promising, mainly due to the breakthrough of novel materials such as graphene. For this reason, numerous research efforts are nowadays targeting THz band nanocommunication and consequently nanonetworking. As it is expected that these trends will continue in the future, we see it beneficial to summarize the current status in these research domains. In this survey, we therefore aim to provide an overview of the current THz nanocommunication and nanonetworking research. Specifically, we discuss the applications envisioned to be supported by nanonetworks operating in the THz band, together with the requirements such applications pose on the underlying nanonetworks. Subsequently, we provide an overview of the current contributions on the different layers of the protocol stack, as well as the available channel models and experimentation tools. Finally, we identify a number of open research challenges and outline several future research directions.

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding of the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and $7.3\times $ , respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.

Traditional industry is experiencing a worldwide evolution with Industry 4.0. Wireless sensor networks (WSNs) have a main role in this evolution as an essential part of data acquisition. The way in which WSNs are powered is one of the main challenges to face if industry wants to achieve the digital transformation. Energy harvesting technologies are one of the possible solutions to this challenge. The main purpose of this paper is to present a novel method to taxonomize knowledge in the field of mechanical energy harvesting to enhance the use of energy harvesting technologies in industrial applications. The methodology is based on the analysis of key parameters and performance metrics for existing technologies. The taxonomy is applied to rail axles in order to select the energy harvesting technology that is more appropriate for this specific location, demonstrating the potential of mechanical energy harvesting technologies (MEHTs) for the railway industry, as a use case of industrial environment. In addition, the taxonomy allows to identify the upcoming challenges for research purposes while analyzing the compatibility among mechanical energy harvesting technologies in order to create hybrid harvesters.

Spaceborne constellations composed by several heterogeneous platforms are an actual solution to undertake Earth Observation missions. However, designing such missions present problems due to the heterogeneity and the multiple design levels that must be considered. In this paper, a high-level methodology to address the design of a spaceborne Earth Observation constellation is outlined. In addition to the framework, this document presents an application of this methodology to a specific use-case, the Agriculture Hydric Stress for a worldwide coverage, and describes its results.

Wireless Network-on-Chip (WNoC) has emerged as a promising alternative to conventional interconnect fabrics at the chip scale. Since WNoCs may imply the close integration of antennas, one of the salient challenges in this scenario is the management of coupling and interferences. This paper, instead of combating coupling, aims to take advantage of close integration to create arrays within a WNoC. The proposed solution is opportunistic as it attempts to exploit the existing infrastructure to build a simple reconfigurable beamforming scheme. Full-wave simulations show that, despite the effects of lossy silicon and nearby antennas, within-package arrays achieve moderate gains and beamwidths below 90°, a figure which is already relevant in the multiprocessor context.

The design of autonomous operational schemes for distributed, decentralized systems is expected to bring multiple qualities to systems of this kind. One of their instances are Earth-observing swarms of nano-satellites, in which their collective function targets global performance figures. The design of autonomous operations can be modelled as a collective scheduling problem subject to resource constraints. There are many system-wide qualities of interest, such as resiliency, adaptability, responsiveness, among others, that need specific frameworks to characterize the proposed solutions. This paper presents one such design-oriented tool that can evaluate these autonomous organization schemes-potentially for large-scale and highly heterogeneous scenarios with dynamic contexts and multiple time-scales-and illustrates its usage in the evaluation of an autonomous nano-satellite swarm that collectively optimizes revisit times.

Metasurfaces, the two-dimensional counterpart of metamaterials, have caught great attention thanks to their powerful control over electromagnetic waves. Recent times have seen the emergence of a variety of metasurfaces exhibiting not only countless functionalities, but also a reconfigurable or even programmable response. Reconfigurability, however, entails the integration of tuning and control circuits within the metasurface structure and, as this new paradigm moves forward, new reliability challenges may arise. This paper examines, for the first time, the reliability problem in programmable metamaterials by proposing an error model and a general methodology for error analysis. To derive the error model, the causes and potential impact of faults are identified and discussed qualitatively. The methodology is presented and instantiated for beam steering, which constitutes a relevant example for programmable metasurfaces. Results show that performance degradation depends on the type of error and its spatial distribution and that, in beam steering, error rates over 10% can still be considered acceptable.

During these years, novel Distributed Satellite Systems (DSS) have disrupted traditional space segment paradigms. In particular, Federated Satellite Systems and fractionated spacecraft have explored the benefits of interacting satellite networks and are envisioned to improve Earth observation performance while maximizing mission utility. Inter-Satellite Communications capabilities and spacecraft coordination mechanisms are cornerstone aspects that need be designed and evaluated to achieve many of the envisioned DSS characteristics (e.g. in-orbit data services, autonomous mission planning). Given the system complexity, heterogeneity and large-scale, the design of these critical features has to be grounded on simulation-based frameworks. Consequently, this paper presents the design of a highly modular and reconfigurable software that enables the emulation of DSS. The paper motivates the design and discusses its adaptability to future user needs.

A low-quiescent current output-capacitorless class-AB CMOS low-dropout voltage regulator (LDO) capable to source/sink current to/from the load is presented, which is suitable for hybrid or linear-assisted structures utilized in envelope elimination and restoration (EER) applications. The proposed LDO regulator is designed and characterized in 0.18 μm CMOS process to provide a 1 V stable output voltage with 200 mV dropout without any off-chip output capacitor and can deliver a current range of 160 mA between -80 mA and +80 mA to the load, while consumes only 1.8 μA quiescent current.

Traditional industry is experiencing a worldwide development with Industry 4.0. Wireless sensor networks (WSNs) have a main role in this revolution as an essential part of data acquisition. The way in which WSNs are powered is one of the main challenges to face if Industry wants to achieve the digital transformation. Energy harvesting taechnologies are one of the possible solutions to this challenge. The main purpose of this paper is to present a novel method to taxonomize knowledge in the field of mechanical energy harvesting in order to enhance the use of energy harvesting technologies for industrial applications. Additionally, the taxonomy allows to identify upcoming challenges for research purposes.

Metasurfaces, ultrathin and planar electromagnetic devices with sub-wavelength unit cells, have recently attracted enormous attention for their powerful control over electromagnetic waves, from microwave to visible range. With tunability added to the unit cells, the programmable metasurfaces enable us to benefit from multiple unique functionalities controlled by external stimuli. In this review paper, we will discuss the recent progress in the field of programmable metasurfaces and elaborate on different approaches to realize them, with the tunability from global aspects, to local aspects, and to software-defined metasurfaces.

Tunable metasurfaces are ultra-thin, artificial electromagnetic components that provide engineered and externally adjustable functionalities. The programmable metasurface, the HyperSurFace, concept consists in integrating controllers within the metasurface that interact locally and communicate globally to obtain a given electromagnetic behaviour. Here, we address the design constraints introduced by both functions accommodated by the programmable metasurface, i.e., the desired metasurface operation and the unit cells wireless communication enabling such programmable functionality. The design process for meeting both sets of specifications is thoroughly discussed. Two scenarios for wireless intercell communication are proposed. The first exploits the metasurface layer itself, while the second employs a dedicated communication layer beneath the metasurface backplane. Complexity and performance trade-offs are highlighted.

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. The WNoC paradigm has been extensively analyzed from the physical, network and architecture perspectives assuming mmWave band operation. However, there has not been a comprehensive study at this band for realistic chip packages and, thus, the characteristics of such wireless channel remain not fully understood. This work addresses this issue by accurately modeling a flip-chip package and investigating the wave propagation inside it. Through parametric studies, a locally optimal configuration for 60 GHz WNoC is obtained, showing that chip-wide attenuation below 32.6 dB could be achieved with standard processes. Finally, the applicability of the methodology is discussed for higher bands and other integrated environments such as a Software-Defined Metamaterial (SDM).

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.

Graphene is enabling a plethora of applications in a wide range of fields due to its unique electrical, mechanical, and optical properties. In the realm of wireless communications, graphene shows great promise for the implementation of miniaturized and tunable antennas in the terahertz band. These unique advantages open the door to new reconfigurable antenna structures which, in turn, enable novel communication protocols at different levels of the stack. This paper explores both aspects by, first, presenting a terahertz Yagi-Uda-like antenna concept that achieves reconfiguration both in frequency and beam direction simultaneously. Then, a programmable antenna controller design is proposed to expose the reconfigurability to the PHY and MAC layers, and several examples of its applicability are given. The performance and cost of the proposed scheme is evaluated through full-wave simulations and comparative analysis, demonstrating reconfigurability at nanosecond granularity with overheads below 0.02 mm2and 0.2 mW.

On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.

Magnetic resonance wireless power transfer (WPT) is a very promising technology for a wide range of applications. The transmission range and efficiency of wireless power transfer have been reasonably enhanced by resonating transmitter and receiver coil at a common frequency. The transmitter and receiver sides have to be perfectly tuned, otherwise power transfer capability is greatly reduced. This paper discusses the detuning effect of parallel compensated receivers, and thereof a novel self-tuning method and related circuit topology and control is proposed and characterized in the system application. The proposed method is based on the concept of switch-mode gyrator emulating variable lossless inductors oriented to enable self-tunability in WPT receivers.

This paper presents an output-capacitorless class-AB low-dropout (LDO) regulator with load current sinking and sourcing ability. The proposed LDO consists of two complementary pass transistors, controlled using a level shifter technique. The transient improvement section applied to the gates of the pass devices enhances the transient performance of the LDO. The proposed LDO is designed in TSMC 0.18 μm CMOS process with input and output voltages of 1.2-2.5 V and 1 V, respectively, 10 pF output capacitor, and quiescent current of 3.14 μA, and is capable to sink and source maximum load currents of ±100 mA, giving the current efficiency of 99.99%.

In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

This work presents the emulation of tunable switch-mode inductive elements for power converters applications. Such elements are based on the concept of ideal loss-free realization by means of switch-mode circuits. A gyrator-based approach for synthesizing inductors is demonstrated. The value of the emulated inductance could be tuned by using appropriate control which would help to alleviate common undesirable properties of conventional passive implementations such as tolerance and value change over temperature and time. This approach enables monolithic circuits composed of semiconductor devices and small inductors/capacitors to be used to emulate large reactive components as a step forward for enhanced power converter miniaturization and integration.

This paper presents an output-capacitorless low-dropout (LDO) regulator based on improved flipped voltage follower power stage for use in power management circuits. A new error amplifier (EA) structure, named as gain-bandwidth enhanced EA, is embedded in the LDO regulator. The LDO regulator is designed for the input and output voltages of 1.2 V and 1 V, respectively. Fast transients, low overshoot and undershoot, and low quiescent current of 6 μΛ are achieved for the proposed circuit. The LDO regulator is designed for maximum load current of 50 mA, achieving the current and power efficiencies of 99.99% and 83.3%, respectively. Additionally, up to 131 pF capacitance is used in the proposed LDO structure. The proposed circuit is designed and verified in HSPICE in TSMC 0.18 μm mixed signal CMOS process.

In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a new class-AB LDO regulator instead of the conventional linear one (based on a push-pull output stage) in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter. Thus, the proposal achieves higher power efficiency rather than the conventional linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. In addition, the circuit provides a lower output ripple and better transient response. A comparison analysis is done with regards to the considered performance indexes between the proposed structure and linear-assisted buck converter, and the results are validated in HSPICE in a 0.35 μm CMOS process.

Wireless RF power transmission from dedicated Energy Transmitters (ETs) is emerging as a promising approach to enable battery-less wireless networked sensor systems. However, when data communication and RF energy recharging occur in-band, sharing the RF medium and devoting separate access times for both operations raises architectural and protocol level challenges. This paper proposes a novel method of concurrent transmission of data and energy to solve this problem, allowing ETs to transmit energy and sensors to transmit data in the same band synchronously. Our key idea concerns devising a physical layer modulation scheme that allows the data transmitting node to introduce variations in the envelope of the energy signal at the intended recipient. We implemented a proof-of-concept receiver, modeled and validated through extensive experimentation. We then propose a new physical layer mechanism for guaranteed successful delivery of information in a point-to-point link. Quantitative results demonstrate the feasibility of joint energy-data transfer, along with its associated benefits and tradeoffs.

Simultaneous Wireless Information and Power Transmission (SWIPT) has been proposed as a feasible solution to enable joint power and data transfer for the nodes of a battery-less wireless networked sensor system. Different from existing approaches, where the incident energy is split between decoding and harvesting blocks at the receiver chain, this paper describes the design and implementation of an all-digital receiver circuit. We leverage the internal control signals of the circuit, targeting ultra-low power consumption, low bit-rate applications in SWIPT. A proof-of-concept receiver is modeled, implemented using off-the-shelf hardware, and validated through extensive experiments. Quantitative results demonstrate the benefits of this joint energy-data reception approach through a single receiver chain, offering bit-rates of 400 bps.

This paper introduces the concept of switch-mode tunable emulated reactive networks. The idea of implementing reactive networks based on the theory of gyrators is proposed and characterized in an application-driven design-oriented context. By means of using switch-mode power processing converters to synthesize gyrators, small capacitors or inductors are effectively multiplied to emulate larger ideally lossless reactive elements. The proposed idea enables to electronically tune the values of reactive elements by means of timing control variables. The proposed tunable reactive networks target many potential applications such as tunable-front-ends for energy harvesting, electronic compensating active power filters, and tunable-front-ends for wireless power transfer links.

This paper deals with a circuit proposal along with theoretical analysis to provide a solution for enhancing the stability and transient performance of external capacitorless low-dropout regulators (CL-LDOs) by segmenting the pass transistor to smaller sizes. The stability and transient analysis is carried out on the CL-LDO with two different size-segmented pass transistors in comparison with the conventional CL-LDO with single large size pass device. The analysis shows that the pass transistor segmentation leads to better stability, i.e., greater phase margin especially at no-load and light-load conditions, wider bandwidth, and improved transient behavior, i.e., lower settling time and output voltage deviations due to the load transients. The aforementioned topologies are modeled and validated in HSPICE using a 0.35 μm CMOS process, and the results are in conformity with the analytical statements.

Multisource energy harvesters are a promising, robust alternative to power the future Internet of Nano Things (IoNT), since the network elements can maintain their operation regardless of the fact that one of its energy sources might be temporarily unavailable. Interestingly, and less explored, when the energy availability of the energy sources present large temporal variations, combining multiple energy sources reduce the overall sparsity. As a result, the performance of a multiple energy harvester powered device is significantly better compared to a single energy source even if they harvest the same amount of energy. In this context, a framework to model and characterize the area for multiple source energy harvesting (EH) powered systems is proposed. This framework takes advantage of this improvement in performance to provide the optimal amount of energy harvesters, the requirements of each energy harvester, and the required energy buffer capacity, such that the overall area or volume is minimized. On top of these results, self-tunable energy harvesters are explored as a solution and compared to multisource EH platforms. As the results show, by conducting a joint design of the energy harvesters and the energy buffer, the overall area or volume of an EH powered device can be significantly reduced.

Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors with hundreds or thousands of cores. The main reason is that the performance of such networks drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.

Wireless RF power transmission promises battery-less, resilient, and perpetual wireless sensor networks. Through the action of controllable Energy Transmitters (ETs) that operate at-a- distance, the sensors can be re-charged by harvesting the radiated RF energy. However, both the charging rate and effective charging range of the ETs are limited, and thus multiple ETs are required to cover large areas. While this action increases the amount of wireless energy injected into the network, there are certain areas where the RF energy combines destructively. To address this problem, we propose a duty-cycled random- phase multiple access (DRAMA). Non-intuitively, our approach relies on deliberately generating random interferences, both destructive and constructive, at the destination nodes. We demonstrate that DRAMA optimizes the power conversion efficiency, and the total amount of energy harvested. Through real-testbed experiments, we prove that our proposed scheme provides significant advantages over the current state of the art in our considered scenario, as it requires up to 70% less input RF power to recharge the energy buffer of the sensor in the same time.

Resonant Inductive Coupling Wireless Power Transfer is a key technology to provide an efficient and harmless wireless energy channel to consumer electronics, biomedical implants and wireless sensor networks. However, current applications are limited to point-to-point links and do not explore the capabilities of Multi-Node Resonant Inductive Coupling Wireless Power Transfer Systems. In such a system, the multi-path relaying effect between different nodes could effectively improve the performance of the link in terms of power transferred to the load and power transfer efficiency. However, depending on the impedance and resonant frequency of the nodes that generate the multi-path effect, these nodes could also act as interfering objects, therefore a) making the transmitter and/or receiver act as a pass-band filter and b) loosing part of the transmitter magnetic field through coupling to the interfering node. In this article, a circuit-based analytical model that predicts the behavior of a Multi-Node Resonant Inductive Coupling link is proposed and used to perform a design-space exploration of the multi-path relaying effect in RIC Wireless Power Transfer Systems.

Resonant Inductive Coupling Wireless Power Transfer is a leading field of research due to the growing number of applications that can benefit from this technology: from biomedical implants to consumer electronics, fractionated spacecraft and electric vehicles, amongst others. However, applications are currently limited to point-to-point-links and do not target Single Input — Multiple Output (SIMO) scenarios. New challenges and applications of Resonant Non-Radiative Wireless Power Transfer emphasize the necessity to explore, predict and assess the behavior of RIC-WPT in SIMO links. Moreover, new systemlevel metrics have to be derived to study the scalability of SIMO Wireless Power Transfer applications and to provide design guidelines for these systems. In this article a Single Input — Multiple Output RIC-WPT System is modeled analytically from a circuit-centric point of view and validated using a Finite Element Field Solver (FEKO). The analytical model and associated closed formulation is finally used to derive system-level metrics to predict the behavior and scalability of RIC SIMO Systems and the results are showcased for an assymetric SIMO scenario.

This paper presents a design-oriented characterization of ring-oscillator (RO) circuits based on complementary-inverters (INVs) implemented with graphene-FET (GFET) devices. A large-signal GFET compact model based on drift-diffusion transport is benchmarked at the circuit level against a second GFET compact model based on virtual source. Transient-based simulations of a 3-cell RO yield performance metrics in terms of operating frequency and voltage dynamic range. Against these metrics, a comprehensive design space exploration covering as input design variables parameters as GFET gate-oxide thickness tOXand channel-length L is presented. Methodologically, the work presents a general-purpose design framework, illustrated for ROs, which establishes a vertical circuit-device co-design environment. Its double-fold outcome is to provide guidelines both to bottom-up dimension and size the circuit, as well as top-down refine GFET device models and in turn GFET technology.

This paper presents a RIC-WPT system with class-E inverter and class-DE rectifier along with its analytical design procedure. By using the class-E inverter as a transmitter and the class-DE rectifier as a receiver, the designed WPT system can achieve a high power-delivery efficiency because of the class-E ZVS/ZDS conditions in both the inverter and the rectifier. In the experimental results, the system achieved 73.0 % overall efficiency at 9.87 W (50 Ω) output power, coil distance 10 cm, and 1 MHz operating frequency. The experimental results showed good agreement with the design specifications, which indicates the validity of the design procedure.

The cost of broadcast has been constraining the design of manycore processors and of the algorithms that run upon them. However, as on-chip RF technologies allow the design of small-footprint and high-bandwidth antennas and transceivers, native low-latency (a few clock cycles) and low-power (a few pJ/bit) broadcast support through wireless communication can be envisaged. In this paper, we analyze the main networking design aspects and challenges of Broadcast-oriented Wireless Network-on-Chip (BoWNoC), which are basically reduced to the development of Medium Access Control (MAC) protocols able to handle hundreds of cores. We evaluate the broadcast performance and scalability of different MAC designs, to then discuss the impact that the proposed paradigm could exert on the performance, scalability and programmability of future manycore architectures, programming models and parallel algorithms.

The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the many core era. Multicast support represents a particular yet relevant case within this context and has been the focus of different research efforts, mainly due to the poor performance of NoCs in the presence of this increasingly important type of traffic. However, most of the proposed schemes have been evaluated using synthetic traffic or within a full system, which is either unrealistic or costly. While traffic models would allow to better assess their performance, existing proposals do not distinguish between unicast and multicast flows and often are bound to a given number of cores. In this paper, a trace-based multicast traffic characterization is presented with the aim to provide guidelines for the modeling of multicast communications in many core settings. To this end, the scaling trends of aspects such as the multicast traffic intensity or the spatiotemporal injection distribution are analyzed. The novelty of this work resides both on its scalability-oriented approach and on the use of correlation metrics to evaluate potential prediction opportunities.

Graphene is enabling a plethora of applications in a wide range of fields due to its unique electrical, mechanical, and optical properties. Among them, graphene-based plasmonic miniaturized antennas (or shortly named, graphennas) are garnering growing interest in the field of communications. In light of their reduced size, in the micrometric range, and an expected radiation frequency of a few terahertz, graphennas offer means for the implementation of ultra-short-range wireless communications. Motivated by their high radiation frequency and potentially wideband nature, this paper presents a methodology for the time-domain characterization and evaluation of graphennas. The proposed framework is highly vertical, as it aims to build a bridge between technological aspects, antenna design, and communications. Using this approach, qualitative and quantitative analyses of a particular case of graphenna are carried out as a function of two critical design parameters, namely, chemical potential and carrier mobility. The results are then compared to the performance of equivalent metallic antennas. Finally, the suitability of graphennas for ultra-short-range communications is briefly discussed.

Graphene is a promising material which has been proposed to build graphene plasmonic miniaturized antennas, or graphennas, which show excellent conditions for the propagation of Surface Plasmon Polariton (SPP) waves in the terahertz band. Due to their small size of just a few micrometers, graphennas allow the implementation of wireless communications among nanosystems, leading to a novel paradigm known as Graphene-enabled Wireless Communications (GWC). In this paper, an analytical framework is developed to evaluate how the channel capacity of a GWC system scales as its dimensions shrink. In particular, we study how the unique propagation of SPP waves in graphennas will impact the channel capacity. Next, we further compare these results with respect to the case when metallic antennas are used, in which these plasmonic effects do not appear. In addition, asymptotic expressions for the channel capacity are derived in the limit when the system dimensions tend to zero. In this scenario, necessary conditions to ensure the feasibility of GWC networks are found. Finally, using these conditions, new guidelines are derived to explore the scalability of various parameters, such as transmission range and transmitted power. These results may be helpful for designers of future GWC systems and networks.

Networks-on-chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of wireless network-on-chip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of: 1) the number of cores within the chip, and 2) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity), and network-level considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication.

Coupled magnetic resonance is considered to be a key enabling technology for mid-range wireless power transfer. Models and systems have hitherto considered linear resonators as underlying dynamics, thereby limiting practical deployability due to the extreme sensitivity in front of parameter mismatch and resonance detuning. In this work, structural nonlinear modeling of constituent elements of the resonant link-resonant coils- is considered to unveil the existence of nonlinear dynamic regimes. The methodology considered to explore the nonlinear behavior is based on a behavioral model consisting of state equations, Floquet theory and Filippov method to study the stability of the periodic regime through the associated monodromy matrix. The ultimate aim of the investigation is a design-oriented parameter space exploration which characterizes the border of occurrence of the different dynamic modes in wireless power transfer links.

Recent research in wireless power transfer (WPT) using resonant inductive coupling has demonstrated very high efficiencies at large distances compared to the transmitting element dimensions, thereby increasing the number of potential applications of WPT. Since resonant inductive coupling is a very multidisciplinary field of research, different approaches have been proposed to predict the behaviour of these systems from the physical theory of resonators (coupled-mode theory) and circuit theory. Although the equivalence of these models for a point-to-point link has already been studied together with the performance metrics Power Transferred to the Load (PTL) and Power Transfer Efficiency (PTE), the new challenges and applications of this technology emphasize the necessity of analytical models to predict and assess the behavior of Multiple Input - Multiple Output (MIMO) links. In this article we revisit the current analytical models from the MIMO perspective, derive the analytical equations for the equivalent performance metrics PTE and PTL and demonstrate how to maximize them in a non-radiative resonant wireless power transfer link from a circuit-centric point of view, providing design guidelines in terms of optimal source and load impedances. This work concludes with a prospective discussion on open challenges of WPT.

Multi-source energy harvesters are gaining interest as a robust alternative to power wireless sensors, since the sensor node can maintain its operation regardless of the fact that one of its energy sources might be temporarily unavailable. Interestingly, and less explored, when the energy availability of the energy sources present large temporal variations, combining multiple energy sources reduce the overall sparsity. As a result, the performance of a multiple energy harvester powered sensor node is significantly better compared to a single energy source which harvests the same amount of energy. In this context, a circuit area optimization framework for multiple source energy harvesting powered systems is proposed. This framework takes advantage of this improvement in performance to provide the optimal amount of energy harvesters, the requirements of each energy harvester and the required energy buffer capacity, such that the overall area or volume is minimized. As the results show, by conducting a joint design of the energy harvesters and the energy buffer, the overall area or volume of a sensor node can be significantly reduced.

This paper presents a resonant inductive coupling wireless power transfer (RIC-WPT) system with a class-E2dc-dc converter along with its analytical design procedure. By using the class-E inverter as a transmitter and the class-E rectifier as a receiver, the designed WPT system can achieve a high power-conversion efficiency because of the class-E ZVS/ZDS conditions satisfied in both the inverter and the rectifier. In the simulation results, the system achieved 65.9 % overall efficiency at 5 W (50 Ω) output power, coil distance 30 cm, and 5 MHz operating frequency. Additionally, the simulation results showed good agreement with the design specifications, which indicates the validity of the design procedure.

Multicast on-chip communications are expected to become an important concern as the number of cores grows and we reach the manycore era. The increasing importance such traffic flows directly contrasts with the diminishing multicast performance of current Network-on-Chip (NoC) designs, and has lead to a surge of research works that seek to improve on-chip multicast support. Within this context, one-to-many traffic models may become useful for the early-stage design and evaluation of these proposals. However, existing models do not distinguish between unicast and multicast flows and often do not consider different multiprocessor sizes. To bridge this gap, a multicast scalability analysis is presented, aiming to provide tools for the modeling of multicast communications for NoC design and evaluation purposes.

Nonlinearities have been shown to play an important role in increasing the extracted energy of energy harvesting devices at the macro and micro scales. Vibration-based energy harvesting on the nano scale has also received attention. In this paper, we characterize the nonlinear dynamical behavior of a strained nanostructured graphene for its potential use in energy harvesting applications. A compressed vibrating membrane graphene sheet free from any external excitation is first studied. We present a continuous time dynamical model of the system in the form of a double-well single degree of freedom system. Equilibrium points are obtained and their stability analysis is carried out. Then, random vibrations are considered as the main ambient energy source for the system and its performances in terms of the well occupation zones, RMS value of the position, and the corresponding energy harvested are presented in the steady state non-equilibrium regime when the noise level is considered as a control parameter. From this model, nonlinear analysis is carried out by computing state space trajectories, probability density and FFT spectra under a deterministic excitation. The ultimate goal of this parameter space exploration based upon a behavioral model is to provide design-oriented guidelines for engineering graphene-based mechanical harvesters.

Resonant Inductive Coupling Wireless Power Transfer is a key technology to provide an efficient and harmless wireless energy channel to consumer electronics, biomedical implants and wireless sensor networks. However, there are two factors that are limiting the applicability of this technology: the effects of distance variation between transmitter and receiver and the effects of interfering objects. While distance variation in WPT has been thoroughly studied, the effects of interfering objects in resonant inductive coupling links are still unclear. In this article we propose a new circuit-based analytical model that predicts the behavior of a resonant inductive coupled link in the presence of interfering objects and verify the obtained results with a Finite Element Field Solver.

Recent research in wireless power transfer (WPT) using resonant inductive coupling has demonstrated very high efficiencies (above 40%) at large distances compared to the transmitting element dimensions, thereby exponentially increasing the number of potential applications of WPT. Since resonant inductive coupling is a very multidisciplinary field, different approaches have been proposed to predict the behaviour of these systems from the physical theory of resonators (coupled-mode theory), reflected load theory and circuit theory. Also, there is in this field a heterogeneous definition of metrics without a clear optimization process. In this article we unify the different metrics and demonstrate how to maximize the power transfer efficiency in a non-radiative resonant wireless power transfer link from a circuit-centric point of view providing design guidelines in terms of optimal load impedance, optimal source impedance and optimal distance between coils.

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.

Nanonetworks, the interconnection of nanosystems, are envisaged to greatly expand the applications of nanotechnology in the biomedical, environmental and industrial fields. However, it is still not clear how these nanosystems will communicate among them. This work considers a scenario of Diffusion-based Molecular Communication (DMC), a promising paradigm that has been recently proposed to implement nanonetworks. In a DMC network, transmitters encode information by the emission of molecules which diffuse throughout the medium, eventually reaching the receiver locations. In this scenario, a pulse-based modulation scheme is proposed and two techniques for the detection of the molecular pulses, namely, amplitude detection and energy detection, are compared. In order to evaluate the performance of DMC using both detection schemes, the most important communication metrics in each case are identified. Their analytical expressions are obtained and validated by simulation. Finally, the scalability of the obtained performance evaluation metrics in both detection techniques is compared in order to determine their suitability to particular DMC scenarios. Energy detection is found to be more suitable when the transmission distance constitutes a bottleneck in the performance of the network, whereas amplitude detection will allow achieving a higher transmission rate in the cases where the transmission distance is not a limitation. These results provide interesting insights which may serve designers as a guide to implement future DMC networks.

Nanotechnology is enabling the development of devices in a scale ranging from a few to hundreds of nanometers. The nanonetworks that result from interconnecting these devices greatly expand the possible applications, by increasing the complexity and range of operation of the system. Molecular communication is regarded as a promising way to realize this interconnection in a bio-compatible and energy efficient manner, enabling its use in biomedical applications. However, the transmission range of molecular signals is strongly limited due to the large and inherent losses of the diffusion process. In this paper, we propose the employment of Quorum Sensing so as to achieve cooperative amplification of a given signal. By means of Quorum Sensing, we aim to synchronize the course of action of a certain number of emitters, which will transmit the same signal. Under the assumption of a linear channel, such signal will be amplified and thus the transmission range will be consequently extended. Finally, we validate our proposal through simulation.

Graphene-enabled wireless communications set the Terahertz Band as the frequency band of operation of future nanodevices (0.1-10 THz). Amongst others, femtosecond-long pulse-based modulation schemes have been recently proposed to enable the communication among nanodevices. Within this context, a receiver architecture suitable for nanodevices must be ultra compact, must have high sensitivity and must be ultra-low power. Unfortunately, common receiver architectures used in other communication schemes, such as IR-UWB, show a strong compromise between low complexity and performance. In this paper, a novel receiver architecture for pulse-based communication based on a Continuous-time Moving Average (CTMA) symbol detection scheme is presented. This scheme bases its symbol decision on the received signal power maximum peak after the CTMA, which is implemented with a single low-pass filter. Moreover, an analytical model for the symbol detection is provided and it is quantitatively shown that the proposed CTMA scheme outperforms previous symbol detection schemes for pulse-based modulations in terms of Symbol Error Rate (SER). The low complexity and relaxed synchronization needed for this symbol detector makes this structure specially suited for the development of future transceivers for nano-devices.

Digital control of power converters has been an area of considerable research interest in recent times. One of the problems which arises in these systems is that of the limit cycle oscillations that occur due to quantization in the feedback loop. This paper investigates the limit cycle oscillations that occur in the digitally controlled version of the buck converter with a proportional-integral controller. The amplitude and frequency of the oscillations that may occur on two duty cycle levels are investigated and related to the controller gain parameters. The analysis shows that it is not possible to guarantee that limit cycle oscillations on two levels will not occur simply by adjusting the gain parameters, and yields a condition which will prevent oscillations on two levels from occurring.

Wireless Sensor Networks (WSN) present a pending challenge for a complete deployability due to energy requirements. The Self-Powered WSN approach aims to extend the sensor node life by means of Energy Harvesting. The harvested energy presents an erratic behavior in both time and frequency. In this paper, a new concept of switch-mode electronically tunable band-pass filters is presented to adaptively follow the power source variations and to maximize the power transfer. To implement these switch-mode filters, three alternatives are presented. These filter topologies are modeled and evaluated. Additionally, some design guidelines are provided. The results show how these high efficiency topologies present a band-pass behavior whose center frequency can be electronically tuned over one decade. The results target the integration of these high-efficiency switch-mode band-pass filters into the future harvesting front-ends.

In this paper a closed-form stability condition is obtained for predicting the boundary of fast-scale instability in a buck switching power converter. This design-oriented condition is obtained from the discrete-time model and it is validated by means of numerical simulation under different cases, including only the voltage-mode loop, current-mode along with voltage-mode loop open or closed, or adding an external compensating ramp. The availability of such design-oriented expression allows to understand the effect of the different parameters of the regulator upon the stability boundary along with facilitating the design and synthesis of new controllers to avoid these instabilities.

In this paper a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) is presented. The utilized CFA consists of an open-loop voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100 mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process reveal that the maximum output voltage deviation of the proposed LDO for 0-100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than -56dB over the entire load current range.

Diffusion-based molecular communication is a promising bio-inspired paradigm to implement nanonetworks, i.e., the interconnection of nanomachines. The peculiarities of the physical channel in diffusion-based molecular communication require the development of novel models, architectures and protocols for this new scenario, which need to be validated by simulation. With this purpose, we present N3Sim, a simulation framework for diffusion-based molecular communication. N3Sim allows to simulate scenarios where transmitters encode the information by releasing molecules into the medium, thus varying their local concentration. N3Sim models the movement of these molecules according to Brownian dynamics, and it also takes into account their inertia and the interactions among them. Receivers decode the information by sensing the particle concentration in their neighborhood. The benefits of N3Sim are multiple: the validation of channel models for molecular communication and the evaluation of novel modulation schemes are just a few examples.

The type of transversal competences and skills to be acquired by EE students is in open debate. It is argued in this paper that beyond core technical skills and soft skills, the competences of Conceiving, Designing, Implementing and Operating Circuits and Systems are key for a comprehensive electrical engineering education. CAS- centric learning activities and methodologies oriented to expose the student to such skills are discussed. This description is carried out both at curriculum architecture level as well as at course level, in the framework of the CDIO approach, an engineering education methodology which considers design-oriented analysis techniques included in an integral project-based learning methodology.

A mixed-signal continuous-time-processing standard CMOS implementation of an asynchronous sigma-delta modulator aimed to drive a switching amplifier operating as an on-chip wideband adaptive power supply is presented in this work. The paper first briefly discusses the fundamental limit tracking capabilities of a two-level switching signal to inband- error-free track a bandlimited signal with minimum average switching frequency. It is argued the adequacy of an adaptive asynchronous sigma-delta modulator (AAΣΔ) to approximate such fundamental characteristics. The second part of the paper presents mixed-signal design details of the various subcircuits implementing a CMOS low-power digitally-programmable AAΣΔ modulator, with 7 MHz average switching frequency operation and 1000 μm × 640 μm area occupancy.

This work presents a switching converter topology which can boost and step down the supply voltage and can deliver both positive and negative voltages to a grounded load (bipolar converter topology with non-floating output). This topology, which uses five switches to perform the power conversion, is mostly intended for switching amplifiers, especially for applications which require both boosting and inverting the supply voltage (to supply bipolar voltage signals), and/or EMI-sensitive applications. Using a single-stage switching amplifier based on this 5-switch topology, it is feasible to supply a grounded load with a symmetrical bipolar voltage signal whose magnitude extends up to several times the magnitude of the supply voltage.

This work presents the first design and modelling of bonding-wire-based triangular spiral inductors (Fig. 1), targeting their application to on-chip switching power converters. It is demonstrated that the equilateral triangular shape compared to other polygonal shapes best balances the inductive density as well as the total Equivalent Series Resistance (ESR). Afterwards, a design procedure is presented in order to optimize the inductor design, in terms of ESR and occupied area reduction. Finally, finite-elements simulation results of an optimized design (27 nH, 1 Ω) are presented to validate the proposed expressions.

In space applications, system designs involve a particularly thorough assessment of performance, reliability and stability, as failure cost increases very significantly at each design stage. This effort has to be stressed when evaluating the feasibility of an innovative concept such as an In-Space Wireless Power Transmission (WPT) link. In this context, this work addresses modelling/characterizing the relationships between the input design variables at subsystem level upon complete system-level performance metrics, thereby stablishing a translayer bridge between different system levels of a WPT link based on microwave RF power. The proposed design-oriented modelling framework allows to derive optimum design, which is of particular interest if a comparison of different alternative WPT methods is to be eventually addressed. The microwave WPT link is finally designed by solving the convex optimization problem of maximizing a set of target performance metrics compressed in a single merit figure, considering as the input design space the open design variables associated to the subsystem descriptions. The presented approach yields a design showing the feasibility of the WPT link with a required power of 100W from 0 to 100 meters with an efficiency range from 15% to 45%.

This work proposes a switching policy for multi-level full-bridge switching power converters and analyses their performance by driving them with a multi-level PWM modulation, targeting high-efficiency power amplifiers. Unlike conventional policies, which generate the output voltage levels only from the values of the supply voltages, this enhanced policy also uses the values of the voltage difference between supply voltages to generate additional output voltage levels, therefore maximising the number of output voltage levels for a given set of supply voltages and connection switches. Simulation results show that, when tracking a band-limited signal, the proposed switching policy can reduce the power of the high-frequency spectral content from 21% to 11% by upgrading a 5-level amplifier to a 7-level amplifier without adding supply voltages or connection switches.

The Takagi-Sugeno (TSK) fuzzy model has been extensively used in control applications because of its capability to efficiently approximate multidimensional characteristics. Its application to model circuits and devices has been hitherto reduced, despite its potential benefits. This work is devoted to model by means of TSK scheme the nonlinear characteristics of power MOSFET capacitances to evaluate its impact in the efficiency of Voltage Regulator Modules (VRM) targeting microprocessor supply. A systematic synthesis procedure is proposed to derive the TSK model from experimental data. Implementation of the fuzzy model in a general-purpose circuit simulator is included and its comparison with a look-up-table is discussed.

Due to the increase of required bandwidth, the newer generation of communication systems uses spectrum-efficient digital modulations that involve non-constant envelope RF signals. A technique that potentially can concurrently provide high efficiency and linearity is the Envelope Elimination and Restoration (EER) transmitter architecture which is based on the decomposition of the transmitted signal in a broadband baseband envelope (processed by an envelope-tracking switching power converter) and a narrowband phase-modulated signal (processed by a class-E switch-mode 802.11a WLAN standard RFPA) and the subsequent restoration (through wideband adaptive RF PA supply). In this work, a behavioral system-level characterization of how circuit-level effects (namely limited bandwidth and switching effects) affect the overall communication system performance metrics (characterized by spectra, eye diagrams, signal constellations, EVM and BER) of a 802.11a WLAN system is presented.

The purpose of this paper is the synthesis from the frequency domain standpoint of a controller for switching power converters with the aim to eliminate bifurcation and chaotic behavior. Firstly the paper analyzes the frequency response of previous delay-based chaos controllers unveiling that they are based in comb-filtering at multiples of the sub-harmonic half of the switching frequency. Secondly, chaos control is explored by using both a single notch filter and a bandstop filter at half of the switching frequency. It is demonstrated that the latter achieves chaos rejection while being an implementation-aware simplification of delay-based methods.

This work addresses the analysis and characterisation of an improved asynchronous Σ-Δ modulation, targeting modulating methods for switching amplifiers, dealing with low average switching frequencies (pursuing enhanced efficiency) and high-order output filters (aiming improved reconstruction processes). This work considers bandlimited random signals, which appropriately model actual communication and audio signals, upgrades the modulator with adaptive capabilities and optimises the output filter. Simulation results show that, tracking a 1MHz-bandlimited random signal and compared with a conventional design based on a 2nd order filter PWM converter, it is feasible to reduce the switching frequency by 62% (from 10MHz down to 3,8MHz) whilst keeping the same tracking error.

In this paper a simplified model based on the exact discrete-time map of a buck switching power converter with proportional control, which captures all its dynamics, allows deriving a closed-form stability condition for predicting fast-scale instability boundary. This condition analytically demonstrates the validity of the recently proposed ripple-based index to predict fast-scale period-doubling, hitherto based on an a priori hypothesis and simulation validation, thereby demonstrating the use of the ripple index as a design-oriented tool. The equivalence of the ripple index to the condition derived from the discrete-time map endorses its use as a means to characterize the complete design space against fast-scale instabilities.

In this paper, a simple, fully digital, asynchronous finite state machine controller for buck-boost power converters is introduced and simulated. With the addition of only two analog voltage comparators and six power MOS switches, the circuit can generate an output voltage that is able to track a dynamic reference with a 1 MHz bandwidth with good efficiency using a 0.35 mum CMOS process. The controller also provides adiabatic charging and discharging of capacitive loads.

This work explores two methods to time-encode continuous-time wideband signals, namely asynchronous Σ-Δ and PWM, targeting modulating methods for buck-based switching power converters operating as wideband power amplifiers. In applications such as polar transmitters or line drivers for Power Line Communications, whose aim is bounding the overall losses, there exists a trade-off involving tracking error and OverSampling Ratio (OSR). This work characterises and compares, in terms of tracking error, the complete design space of modulation depth, OSR and filter cutoff frequency for each encoding method. Moreover, it also characterises an additional dimension in the design space, the effect of using a high-order buck converter. The results from this comparison point-out that low-OSR combined with high-order buck converters, are good candidates to address the challenge of wideband high-efficiency amplifiers.

This paper provides a first exploration of fast-scale stability borders for switching power converters operating as wideband switching amplifiers. Such operation is required in audio amplifiers, envelope trackers in polar RF transmitters and line drivers for Power Line Communications. A buck converter with output voltage proportional feedback in a signal tracking configuration with a sinusoidal reference is considered (Figure 1). The work first characterizes the effect of the classical set of parameters used in regulation stability analysis (output resistance, reactive components, switching frequency, feedback gain), and considers the output voltage to cover the complete dynamic range and hence disappear as a variable in the parametric space. Complementarily, the effect of the ratio of the tracking or baseband frequency to the switching frequency is added as a new variable in the design space indicative of wideband tracking operation. Characterization tools encompass families of time domain simulations as dynamic bifurcation diagrams for the time-varying reference. The paper concludes by exploring the effect of momentarily losing fast-scale stability upon the output signal spectrum, since applications such as adaptive supply of RF power amplifier are subject to strict spectral masks.

This work presents an automatic method and circuit to indirectly detect the inductor-current zero-crossing event in an on- chip switching power buck converter operating under Pulse Frequency Modulation (PFM) and hence in Discontinuous Conduction Mode (DCM). The circuit avoids using a fast comparator, which is power-hungry and the nonideal offset and delay of which impact on zero-crossing and hence on efficiency, by recursively adjusting a time-magnitude by sensing two events occurring in the power plant. The complete mixed-signal 0.25 mum CMOS microelectronic circuit as well as the transistor-level simulation results validating the proposal are presented.

This work addresses a method to automatically adjust the dead-time between the power transistors transitions of a DCM-operated 3-level buck converter to avoid both the body-diode conduction and the shot-through current spike. A feedback loop is used to recursively adjust the dead-time depending on the indirect detection of both events. While the body-diode conduction event is detected by sensing the vxvoltage, the shot-through event is detected by means of an observer of the power switches. The complete microelectronic scheme and layout for a 0.25 mura CMOS technology as well as the transistor-level simulation results validating the proposal are provided.

This paper extends the validity of a ripple-based index able to predict the frontier of fast-scale instability bifurcation in switching power converters, for the whole design-space and for different conduction modes. Hitherto a first validation of the index, based on the approximated ripple level in the PWM modulator, was carried out for a basic proportional voltage feedback PWM buck converter and for L, C, fs, Kpparameters. This article has carried out a complete design-space analysis and has found the stability boundary dependence on converter parameters. Besides, the circuit-based approach has been validated through a comparison between the proposed index and the classical analytical methods based in the linearization of the discrete-time nonlinear map. The paper also proposes improved ripple approximations, by obtaining the exact analytic ripple expression for a buck converter derived from Laplace transform. The index is also validated for a buck converter operating in DCM, through time domain simulations and bifurcation diagrams.

This paper presents a re-examination of conditions for lost of period-1 bifurcation appearance in switching power converters. A unified index based on the ripple level in the PWM modulator is able to predict first occurrence of fast-scale instability. Previous parametric design space explorations have been presented to explore the rich complex behaviour phenomena in switching power converters. The bifurcation-avoiding design-oriented index presented herein allows the designer to collect in a unified index the effect of several circuit parameters, such as input and output voltage, reactive component values and switching frequency, together with feedback parameters. The approach is validated through time domain simulations and bifurcation diagrams for a basic proportional voltage feedback PWM buck converter. Alternative topologies such as multilevel converters and interleaved parallel-connected converters, as well as more practical control methods such as dynamic compensators, current-mode control, and hysteretic control are discussed as well. Proof-of-concept experimental results are reported to demonstrate the approach

An analytical approach is carried out to compare the performance of various diode lumped models for circuit simulators. Both frequency and time domain analysis are applied that justify the need of extending the basic charge-control model to more than a simple charge storage node in order to reduce the highly inaccurate prediction of the distributed diffusion and recombination processes that govern the dynamics of pn-junctions, which can effectively be finer modeled with a single zero-pole representation under certain operating conditions. This in turn allows to more precisely assess the impact of the device switching behavior in the application without compromising the required computation power

The envelope elimination and restoration (EER) technique theoretically allows implementation of linear highly efficient RF power amplifiers, as required for next generation digital communications. One of the key remaining challenges for a successful implementation of the EER technique is the efficient implementation of the switching power converter in charge of amplifying the baseband envelope signal, since bandwidths in the order of several MHz are expected for the envelopes to be tracked, hence requiring very high switching frequencies and thus compromising efficiency. This work investigates the feasibility of the EER technique by studying the impact of the nonidealities associated to the switching power converter, namely its bandwidth and ripple, upon the overall polar amplification EER scheme. Considering a two-tone test input signal, a design space exploration of the distortion associated to both nonideal effects is evaluated in terms of the output spurious-free dynamic range (SFDR). Design criteria for the optimum filtering characteristic and phase compensation between polar paths are derived. The work concludes by exploring the extension of switching power converter design criteria for an actual CDMA modulation signal

PWM buck switching power converters are good candidates for high efficiency power amplification of arbitrary band-limited signals. The correlation between the signal bandwidth and the switching frequency, in turn related to switching losses, imposes practical limits for high bandwidth applications. Stringent specifications appear in such applications as audio amplifiers (kHz signal bandwidths), and lately, in fast envelope tracking power amplifiers (MHz signal bandwidths) for the Envelope Elimination and Restoration technique in polar RF power amplification. Bandwidth limitations in PWM amplifiers are explored in this work by proposing design criteria for obtaining the switching frequency to signal bandwidth ratio (fs/fx) so as to guarantee a given aliasing error. To achieve that purpose, PWM spectra are reviewed for single tone, two-tone and multitone signals. Subsequently, by taking into account the analogy between PWM and FM spectra, bandwidths around the switching frequency are estimated by extending Carson's rule to an arbitrary error. This allows obtaining an extension of the Nyquist criterion for pulse-width modulation. System-level simulation results are reported to validate the analysis, showing that the conventional fs/fxfactor used in the power converter design field might be too conservative

Continuous-time filters (CTF) with automatic tuning loops are nonlinear feedback systems with potential instability. Therefore, the appropriate linear dynamic modeling of the tunable filter should be obtained to assure stability in case an improved design of the loop controllers is to be carried out. With this aim, starting from a general and systematic analysis in order to obtain an equivalent small-signal linearised incremental model, from which transfer functions between output variables and control voltages are derived, the subsequent design of compensated loops with enhanced stability and dynamic performance is proposed. In particular, this modeling allows proposing both a non-adaptive and adaptive controllers with improved stability, together with their implementation. As a demonstrative example of application, the modeling of a particular band-pass CMOS CTF is presented in this paper. Experimental results are shown for a CMOS 0.8-mum technology

This paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, we study the microelectronic analog implementation of physical oscillators, instead of the software computer-simulated implementation. With this aim, the original oscillator has been adapted to a suitable microelectronic form. So as to study the hardware nonlinear oscillators, we propose two macro models, demonstrating that they preserve the synchronization properties. Secondary effects such as mismatch and output delay and their relation to network synchronization are analyzed and discussed. We show the correct operation of the proposed electronic oscillators with simulations and experimental results from a manufactured integrated test circuit. The proposed architecture is intended to perform the scene segmentation stage of an autonomous focal-plane self-contained visual processing system for artificial vision applications.

A sequentiality study for mixed-signal VLSI implementations of neuro/fuzzy feedforward algorithms is presented. Implications of sequential processing and mixed-signal operation are derived. Basic building blocks for sequential mixed-signal neural and fuzzy computing are proposed, and two example sequential processors are described. Feedback from designed processors and subcircuits allows consideration of the technology constraints for analysis and extension to different sequentiality degrees.

The most significant sources of nonlinearity in the MOS resistive circuit behaviour are identified and deeply analysed in this contribution. Their influence on the MRC performance and, therefore, in the circuits containing such structure is evidenced through some examples and evaluated. Some reasonable hints about the way to minimise their undesired effects are provided.