Satellite Internet of Things (IoT) network plays a crucial role in providing global coverage. To improve the efficient utilization of spectral and hardware resources in the satellite communications, integrated sensing and communication (ISAC) has attracted considerable attention. In addition, the greater broadcast nature of the satellite-terrestrial integrated network makes it extremely vulnerable to illegal eavesdropper (Eve). In this paper, we adopt non-orthogonal multiple access (NOMA) to support more users for the ISAC of a low earth orbit satellite system, with well-designed precoding according to whether the channel state information (CSI) of the Eve is perfect to ensure security. First, a joint precoding optimization problem is proposed to maximize the sum secrecy rate (SSR) of multiple users by considering the perfect CSI of the Eve. Then, we formulate a secure precoding optimization problem based on the imperfect CSI of the Eve, aiming to maximize the SSR of multiple users via artificial jamming. To address the non-convexity of the optimization problems, we transform them into the convex ones based on successive convex approximation, which includes Taylor’s approximation, arithmetic-geometric mean inequality, and linear matrix inequality. In addition, semi-definite relaxation and iterative penalty function methods are respectively used to optimize the secure precoding problems in the two cases: perfect CSI and imperfect CSI. Simulation results show that the proposed NOMA-ISAC scheme improves the SSR compared to the traditional time division multiple access while ensuring the sensing performance.

We investigate multi-user physical layer security assisted by an unmanned aerial vehicle (UAV) for multi-beam satellite communications in the presence of an eavesdropper (Eve) within the same beam. In particular, the UAV is exploited as a jammer that deliberately generates artificial noise to confuse Eve. To achieve a positive secrecy rate, we consider a non-orthogonal multiple access (NOMA) scheme with imperfect channel state information at the user and Eve. Specifically, we design a robust precoding algorithm to maximize the minimum achievable secrecy rate that satisfies the quality of service for each user and the NOMA decoding order between legitimate users in each beam. In addition, the algorithm is designed under joint total and per-beam transmit power constraints. We first combine the Bernstein-type inequality, the arithmetic-geometric mean inequality with a semi-definite relaxation iterative algorithm to solve the non-convex problem, and further analyze the complexity of the proposed precoding design. Simulation results show that the algorithm significantly improves the security performance.

As a lightweight method, runtime verification aims to check whether one program execution satisfies a desired property. For online runtime verification, the approach efficiency and property expressiveness are two key points restricting its wide application. In this paper, we propose a distributed network-based parallel runtime verification approach to verifying full regular temporal properties for a suitable subset of C (named by Xd-C) programs in an online manner. With this approach, an Xd-C program is translated into an equivalent Modeling, Simulation and Verification Language (MSVL) program, and a desired property is specified as a Propositional Projection Temporal Logic (PPTL) formula; during the program execution, segments of the generated state sequence are verified in parallel by distributed multi-core machines. Experimental results show that, our approach has a speedup of 2.5X-5.0X over the state-of-art runtime verification approaches and supports full regular temporal properties, meaning that our approach can not only take full advantage of computing and storage resources in a distributed network, but also support more expressive properties.

Existing symbol timing recovery (STR) cannot simultaneously meet the performance requirements of broadband satellite internet for throughput, convergence speed, convergence accuracy, and implementation complexity. Focusing on burst single-carrier communications widely used in broadband satellite systems, we proposed a parallel doubly fed STR algorithm combining feedforward and feedback loop, in which the frequency-domain (FD) prefilter is also used to improve the algorithm’s anti-self-noise capability. The corresponding field programmable gate array (FPGA) implementation with low complexity and highly parallel architecture is then accomplished. Simulation results show that the performance degradation caused by the proposed algorithm is less than 0.03 dB compared with the ideal performance when uncoded bit error rate (BER) equals 1e-4 and 64 quadrature amplitude modulation (QAM) modulation is considered. FPGA verification based on the XC7VX690T chip also shows that with 64 parallel inputs and 64-QAM modulation, the throughput rate of information bit can reach 19.2 Gb/s for our design with utilization of 17% look-up tables (LUTs) and 20% digital signal processing (DSP), respectively.

With the rapid development of various services in wireless communications, spectrum resource has become increasingly valuable. Faster than Nyquist (FTN) signaling, proposed in the 1970s, is a promising paradigm for improving spectrum utilization. This paper proposes the variable-packing-ratio (VPR)-based transmissions for high spectrum efficiency (SE) and security, respectively. Aided by deep learning (DL)-based estimation, the proposed scheme for high SE can achieve a higher capacity than the conventional Nyquist-criterion transmission with negligible modification to existing communication paradigms (e.g., spectrum allocation or frame structure). More importantly, for VPR-based secure transmission, a dynamic generation scheme is proposed to produce randomly distributed positions to switch the packing ratio, which can effectively avoid detections and attacks. In addition, we propose a simplified DL-based packing ratio estimation for both of these two scenarios so that the receiver can estimate the packing ratio without any in-band or out-band control messages. Simulation results show that the proposed simplified estimation achieves nearly the same accuracy and convergence speed as the original multi-branch fully-connected structure with a complexity reduction of 20 folds. Finally, we derive the SE of the proposed VPR transmission under different channels. The numerical results validate the correctness of the derivation and demonstrate the SE gains of the VPR scheme beyond conventional Nyquist transmission.

Big data techniques are widely used in various fields. To deal with large data sets efficiently, a new programming framework MapReduce has emerged. Thus, new verification challenges arise to improve the reliability of big data processing. In this article, MapReduce processes are implemented by modeling simulation and verification language programs. Then, several data properties such as data soundness, nonconflict, nonduplication, cooperation, and completeness are taken into account. Moreover, these properties are specified by propositional projection temporal logic formulas. To verify these properties, a runtime verification approach at code level based on unified model checking is employed. In addition, two case studies are conducted to demonstrate our approach: sparse matrix multiplication and tracking down suspected patients of an infectious disease.

The global trends in urbanization have caused many problems, among which Urban Traffic Control (UTC) becomes a priority issue for most big cities in many countries. As traffic demand changes rapidly, appropriate control policies are required to be generated in real time in order to, e.g., minimize congestion to reduce average travel time and air pollution. A practical way to meet the challenge is to build an intelligent control mechanism of road traffic. In this context, automated planning, a powerful and effective technique, can be exploited as an aid to dynamically produce plans to alleviate the problems of UTC. In this paper, we present an approach based on automated planning, in particular temporal planning scheme that aims for producing predictable management strategies of UTC. Meanwhile, a logic style control knowledge is employed to provide useful guidance for the search process in planning. We show the preliminary evaluations on simulation benchmarks closely related to UTC. Experimental results show the feasibility and effectiveness of our approach, compared with the state-of-the-art planners that participate in recent International Planning Competitions.

In this article, we present an approach based on counterexample-guided abstraction refinement to verifying full regular temporal properties of C programs by means of combining both static analysis and dynamic verification. To this end, a desired property is specified by a propositional projection temporal logic formula$p$, and the labeled normal form graph (LNFG) of$\lnot p$is automatically produced. Furthermore, the control flow automaton of the C program is constructed, and an enriched abstract reachability tree is generated under the guidance of the LNFG. Throughout the construction of the eART, whenever a candidate counterexample$cp$is found, a verification input w.r.t$cp$is generated by the SMT solver Z3. Subsequently, the C program is converted into a modeling, simulation, and verification language (MSVL) program$m$, and$\lnot p$is also transformed to an MSVL program$m^{\prime }$. As a result,$m\; \text{and} \;m^{\prime }$is executed to check whether the counterexample is spurious. The$cp$is returned if it is a real counterexample; otherwise, the eART is refined. This process is repeated until no counterexample is found, namely the property is valid, or the counterexample is a real one The proposed approach enables us to not only verify full regular properties of C programs, but also produce precise results, neither false negatives nor false positives. The approach has been implemented in a tool named SDMC. Experiments show that SDMC outperforms the relevant tools available.

In this paper, we propose a shared-memory parallel field-programmable gate array (FPGA) router called ParRA. Basically, ParRA is composed of hybrid partitioning and parallel routing. During the hybrid partitioning, first an FPGA is split into multiple subregions and nets are geographically partitioned into local subsets. As the intersubregion nets usually overlap each other, these nets cannot be routed in parallel. Second, the intersubregion nets are further partitioned into conflict-free subsets. Since each conflict-free subset consists of intersubregion nets do not overlap each other, the nets in the same conflict-free subset can be routed in parallel. In this way, we significantly increase the number of nets that have potential to be routed in parallel. During the parallel routing process, two novel parallel routing strategies are applied to route the nets in conflict-free and local subsets, respectively. With conflict-free subsets, sinks in the same conflict-free subset are routed in parallel while conflict-free subsets are routed one by one. On the contrast, local subsets are routed in parallel while the nets in the same local subset are routed sequentially. With the two different parallel routing strategies, we reduce the interference between threads and balance the workload of threads, which contributes to gain more parallelism. The proposed parallel router provides deterministic routing results. The experimental results show that ParRA achieves an average speedup of $24.3 {\times }$ with 16 threads compared to VPR 7.0, has no negative impact on the quality of results.

Verification of programs at code level has attracted more and more attentions since the cost is high to extract models from source code. Most of approaches available for code level verification are carried out by inserting assertions into programs and then checking whether the assertions are violated. In this way, only safety properties can be verified, however, other temporal properties of programs such as liveness are hard to be verified. To tackle this problem, a novel runtime verification approach, which can verify full regular temporal properties of a program, is proposed in this paper. With this approach, a program to be verified is written in a modeling, simulation and verification language (MSVL) as a program M and a desired property is specified by a propositional projection temporal logic formula P . The negation of the desired property is then translated to an MSVL program M'. Thus, whether M violates P can be checked by evaluating whether there exists an acceptable execution of the new MSVL program “M and M'.” This problem can efficiently be solved with the MSVL compiler where verification cases are generated via dynamic symbolic execution. Further, we adopt parallel mechanism to handle various execution paths of a program for improving the efficiency. The proposed approach has been implemented in a tool called MSV. Experiments show that the performance of MSV outperforms existing tools such as T2, RiTHM, and LTLAutomizer in verifying temporal properties of real-world programs.

A simplified blind equalization algorithm, which can substantially reduce the complexity of hardware implementation of neighborhood-assisted symbol-based decision (N-SBD) algorithm, is proposed for 4096-QAM systems. Two main strategies are adopted in order to achieve our goals. On the one hand, the step function is used to approximate the weighting factor in the conventional N-SBD algorithm for avoiding the complicated exponential calculations. On the other hand, by utilizing the equidistant characteristics for the adjacent symbol coordinates, we derive the formula of the error function again, thus significantly reducing the number of multipliers in implementation. The analysis further shows that, for 4096-QAM signals, the proposed algorithm greatly reduces the implementation complexity at the cost of reducing the convergence speed slightly, whereas it can maintain the mean square error (MSE) performance of the steady-state residual error when compared with the conventional N-SBD algorithm. Simulation results also indicate that both the convergence speed and the steady-state residual error of the proposed algorithm are superior to other blind equalization algorithms, such as the multi-modulus algorithm (MMA) and constellation matched error-based MMA (CME-MMA).

As known, receivers with in-phase and quadrature-phase (I/Q) down conversion, especially direct-conversion architectures' always suffer from I/Q imbalance. I/Q imbalance is caused by amplitude and phase mismatch between I/Q paths. The performance degradation resulting from I/Q imbalance can not be mitigated with simply higher signal to noise ratio (SNR). Thus, I/Q imbalance compensation in digital domain is critical. There are two main contributions in this paper. Firstly, we proposed a blind estimation algorithm for I/Q imbalance parameters based on joint first and second order statistics (FSS) which has a lower complexity than conventional Gaussian maximum likelihood estimation (GMLE). This can be used for further precessing such as equalization in presence of receiver IQ imbalance. In addition, we find out the reason of error floor in conventional I/Q imbalance compensation method based on conjugate signal model (CSM). The proposed joint first order statistics and conjugate signal model (FSCSM) compensation algorithm can reach the ideal bit error rate (BER) performance.

A simplified polarity decision carrier recovery (CR) algorithm is proposed by using the characteristics of 4096-QAM constellation. The proposed scheme, which has the better tradeoff between the performance and the complexity by using a simplified polarity decision phase detector (PD), includes three working modes. The initial frequency offset estimator (IFOE) is firstly applied to estimate the frequency offset in open-loop mode, then the phase-frequency detector (PFD) tracks and compensates the small frequency error in closed-loop mode. A simple decision-directed (DD) PD is finally used for fine phase tracking. Compared with the conventional polarity decision PD, the polarity decision PD in our algorithm needs fewer multipliers, whereas the proposed algorithm can slightly accelerate the convergence speed and maintain the estimation performance. Results show that, the time required for loop convergence is less than 105symbol periods within the range of the normalized frequency offset between -0.09 and 0.09 for 4096-QAM.

In this paper, we present a new field-programmable gate array (FPGA) routing approach on the basis of the PathFinder routing algorithm. During each routing iteration, our approach applies a novel timing-based rerouting strategy to only reroute the illegal paths. At a lower level, each maze expansion is started from the relatively close part of current routing tree to search for the target sink on the routing resource graph. Experimental results demonstrate that on average the proposed approach reduces the routing runtime by 68.5% compared with the timing-driven router in versatile place and route FPGA placement and routing framework, with reduction of 2.5% and 1.4% in critical path delay and wirelength, respectively.

It is of great importance to ensure the correctness and reliability of the scheduling protocol of safety-critical systems since the failure will cause serious damage. This paper analyzes a real time scheduling protocol of the safety-critical system and models it using a Modeling, Simulation and Verification Language program. Then the sufficient and necessary conditions for the schedulability are given. Further, the schedulability and other properties are verified using the MSV toolkit.

Peer-to-Peer(P2P) reputation systems are essential to evaluate the trustworthiness of the nodes in a P2P system. This paper presents a distributed algorithm HP2PSORT based on SORT that enables a node to estimate the trustworthiness of other nodes based on the past interactions and recommendations. In an HP2P network, by using the filtering mechanism, the calculation method of the service trust and the dynamic calculation of the threshold value, we show that HP2PSORT outperforms SORT.

The multi-way relaying networks (MWRNs) are investigated, in which multiple users exchange their information with the help of a relay node. We constraint that all users form a single group to share information with each other by using half-duplex communication mode. For such networks, an universal linear dispersion space-time block code (STBC) is introduced based on amplify-and-forward (AF) relaying protocol. Furthermore, a lower bound of pairwise error probability (PEP) of maximum likelihood (ML) detector is first derived, which reveals that the best-achievable diversity gain function is determined by the signal to noise ratio ρ, the user number K and the antenna number of the relay M, i.e., In ρ/ρM(K-1). Specifically, we design a distributed quasi-orthogonal STBC for the MWRN with K = 3 and demonstrate that the design can obtain a larger diversity gain than those in the one-way and two-way relaying networks by Monte Carlo simulations.

Abstract Since distributed systems are inherently concurrent and asynchronous, it is a challenge for us to verify distributed systems. MSVL is a useful temporal logic programming language and its axiomatic system has been established. However, the axiomatic system of MSVL lacks mechanisms to manage asynchronous communication, which makes it cannot deal with distributed systems. Thus, to verify distributed systems with MSVL in a deductive way, this paper is motivated to extend the axiomatic system of MSVL with new axioms for asynchronous communication. To this end, firstly we formalize state axioms regarding asynchronous communication commands and then prove the soundness and completeness. Further, to demonstrate how the extended axiomatic system of MSVL works for distributed systems, we apply it to the well-known Ricart–Agrawala (RA) algorithm, which is a distributed mutual exclusion algorithm and has an infinite state space. To do this, we model the RA algorithm with MSVL, specify the desired properties and then verify an instance of the RA algorithm with respect to the first-come-first-served property.

Utilizing the recently-developed unique factorization of signals and distributed Alamouti coding scheme, a distributed collaborative Alamouti space-time block code design is presented for a two-way amplify-and-forward (AF) relaying network, where both two sources and the relay are equipped with a single antenna. For such system, two asymptotic pairwise error probability (PEP) formulae are first derived for both fixed-gain AF and variable-gain AF over Rayleigh channels with the maximum likelihood detector. Then, subject to the constraints on a fixed transmission bit rate and unity average transmission energy, the optimal constellation combinations with the optimal energy-scales as the coefficients are attained by minimizing the dominant term of PEP. It is shown that the PEP and the average block error rate of the newly-designed code are superior to those of the conventional distributed Alamouti code.

This paper investigates a complete axiomatic system for propositional projection temporal logic (PPTL). To this end, the syntax, semantics, and logic laws of PPTL are briefly introduced. Further, the normal form of PPTL formulas is presented. Moreover, an axiomatic system of PPTL is formalized. A set of axioms and inference rules are given in details. To assist the proof within the system, some theorems are proved by means of the axioms and rules. In addition, based on the axioms, rules and theorems, the soundness and completeness of the deductive system are proved. Finally, an example is given to illustrate how the axiom system works.