EDBT 2026 Demo / reviewers in the wild / expert
Debabrata Mondal
dblp:28/6526
· DBLP profile ↗
3ranked-venue papers
2as first author
3since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Double-node upset and half select issue tolerant split-14T SRAM for avionics applications
Debabrata Mondal, Syed Farah Naz, Ambika Prasad Shah |
Integr. | 1 |
| 2023 | Radiation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear EnvironmentsabstractExtremely energetic particles prevalent in the nuclear environment make memory cells prone to soft errors. Also, attackers extract secret data of SRAM cells via side-channel attacks (SCAs), and leakage power analysis attacks (LPAs) are a serious threat to security systems. This research indicates an extremely effective radiation-hardened and LPA-resilient (RHLR12T) SRAM cell that is both radiation resistant by design for nuclear applications and LPA-resilient. It offers better speed, enhanced writing stability and higher overlap percentage compared to other considered SRAM cells, such as 6T, Quatro, We-Quatro, and RHMD10T, utilizing 45nm CMOS technology at the supply voltage of 1.0V and 27-C operating temperature. The proposed cell gives 1.141× higher write stability, 1.55× lower write access time, 1.11× increased critical charge and 1.51× better overlap percentage than RHMD10T SRAM cell. Debabrata Mondal, Syed Farah Naz, Ambika Prasad Shah |
ACM Great Lakes Symposium on VLSI | 1 |
| 2023 | Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics ApplicationsabstractThe impact of high-energy particles in space like cosmic rays and alpha particles flips the stored data in an SRAM cell. This paper proposes a highly reliable soft error immune with enhanced critical charge 14T (SIC14T) SRAM cell that is radiation-hardened by design and has an increased critical charge that can withstand both single-event upsets (SEU) and single-event multi-node upsets (SEMNU). We compare the performance of the proposed cell with that of other considered SRAM cells, such as the SRRD12T, RSP14T, SEA14T, and 6T SRAM cell which were simulated in 45-nm CMOS technology in Cadence Virtuoso with a supply voltage of 1V and 27°C operating temperature. Both SEU and SEMNU caused at the storage node of SIC14T are successfully recovered. The proposed SRAM cell has 1.02×, 0.6×, 0.72×, and 4.64× better write stability, read access time, leakage power, and critical charge than the SRRD12T with 1.68× area overhead. Sagheer Ahmed, Jayesh Ambulkar, Debabrata Mondal, Ambika Prasad Shah |
VLSI-SoC | 3 |