A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network-on-chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous processes inside the eFPGAs or locally accelerated by the usage of dedicated microprocessor coprocessors. Each eFPGA on the system can be independently programmed and share logic with the others eFPGAs by intra-communication channels. The architecture is highly scalable since the eFPGA number can be controlled and the reconfigurable platform communication channels are based on a configurable NoC. The silicon area required by the system is 26mm2 in a 90 nm CMOS process. 10x speed ups have been measured on a MP3 playler mapping example.

Recently a lot of multimedia applications have been emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerful computing engine (typically hardware). In this context, programmable HW and dynamic reconfiguration allow novel approaches to the migration of algorithms from SW to HW. Thus, in the frame of the Symbad project, we propose an industrial design flow for reconfigurable SoC. The goal of Symbad consists of developing a system level design platform for hardware and software SoC systems including formal and semi formal verification techniques.

A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.

Consistency, accuracy and efficiency are key aspects for practical usability of a system design flow featuring automatic code generation. Consistency is the property of maintaining the same behaviour at different levels of abstraction through synthesis and refinement, leading to functionally correct implementation. Accuracy is the property of having a good estimation of system performances while evaluating a high-level representation of the system. Efficiency is the property of introducing low overheads and preserving performances at the implementation level. The RTOS is a key element of the link to implementation flow. In this paper, we capture relevant high-level RTOS parameters that allow consistency, accuracy and efficiency to be verified in a top-down approach. Results from performance estimation are compared against measurements on the actual implementation. Experimental results on automatically generated code show design flow consistency, an accuracy error of about 0.66% and an overhead of about 11.8% in term of speed.

A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signals is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standard linear predictive cepstral features. The power consumption of the feature extractor chip is 30 /spl mu/W at 0.9 V.

An algorithm for the linear interpolation of multi-input functions sampled on rectangular grids is presented. A geometric approach is adopted and the mathematics is thoroughly developed. We show that the algorithm is optimum. In fact, when the number n of inputs grows to infinity its computational requirement is O(n log n), which is the same as the lower-bound on the cost of continuous linear interpolation procedures.

This paper describes a VLSI array processor system that has been designed and built for classification problems based on the k-nearest neighbors approach. This architecture is suitable for different pattern recognition applications and is scalable to reduce the computation time. A prototype board with two processors has been built and a software driver has been written showing a speed up of 30 times over a software algorithm running on a Sun SPARC20 workstation.

This article presents a novel approach to the high-level system verification problem based on a hybrid hardware/software virtual emulation tool. Unavailable components or sub-systems are physically replaced on a prototype board by FPGAs whose electrical behavior is driven by software simulations of high-level description models. Such a prototype can smoothly evolve towards the final system as soon as the unavailable parts or the components under manufacturing become available. The simultaneous use of prototyping techniques such as field-programmable circuit boards with software simulation significantly improve the usefulness of our framework. A low-cost verification environment, with multiprocessing and multilanguage capabilities currently in use at University of Bologna, is described.