Phase noise (PN) estimation and compensation is needed for millimeter-wave (mmWave) communication systems to achieve high data rates. Conventional approaches for PN suppression suffer from high computational complexity. To overcome this, we present a low-complexity fully-digital PN suppression for mmWave systems. The key ideas are to exploit the coherence bandwidth of a mmWave system and an approximation of the PN spectrum, based on its Npdominant components. Utilizing these features, the joint estimation problem of PN and channel can be reformulated into a system with the same number of equations and unknowns, which enables low-complexity PN suppression by using a linear minimum mean square error (LMMSE) estimator. Furthermore, we propose a method to reduce the hardware cost of the LMMSE estimator by using a B-bit signal-to-noise ratio (SNR) quantization, which has a very low complexity of O(Np2+ NNp), where N is the number of subcarriers in an OFDM symbol. As a proof-of-concept, a low-cost VLSI architecture is presented to realize the proposed method. The proposed architecture in 28 nm CMOS (post-synthesis) results in an area cost of 258 K gate count and power consumption of 19.3 mW at 250 MHz clock rate.

We consider a multipair two-way relay communication network, where pairs of user devices exchange information via a relay system. The communication between users employs time division duplex, with all users transmitting simultaneously to relays in one time slot and relays sending the processed information to all users in the next time slot. The relay system consists of a large number of single antenna units that can form groups. Within each group, relays exchange channel state information (CSI), signals received in the uplink and signals intended for downlink transmission. On the other hand, per-group CSI and uplink/downlink signals (data) are not exchanged between groups, which perform the data processing completely independently. Assuming that the groups perform zero-forcing in both uplink and downlink, we derive a lower bound for the ergodic sumrate of the described system as a function of the relay group size. By close observation of this lower bound, it is concluded that the sumrate is essentially independent of group size when the group size is much larger than the number of user pairs. This indicates that a very large group of cooperating relays can be substituted by a number of smaller groups, without incurring any significant performance reduction. Moreover, this result implies that relay cooperation is more efficient (in terms of resources spent on cooperation) when several smaller relay groups are used in contrast to a single, large group.

Lattice reduction aided multiple-input and multiple output (MIMO) detection has attracted significant attention recently due to its low complexity and excellent error rate performance. The most popular lattice reduction algorithms are the Lenstra-Lenstra-Lovász algorithm and Seysen's algorithm, although the former has received much more attention than the latter. In this work, we present a simplification to Seysen's lattice reduction algorithm, which reduces the periteration computational complexity from quadratic to linear with a small degradation in the quality of the resulting reduced lattice. Moreover, we present an efficient VLSI architecture which demonstrates the advantages of the proposed algorithm and can achieve a throughput of up to 91 Mmatrices/s at an operating frequency of 1 GHz.

With technology scaling enabling integration of billions of transistors on a single processor core, deploying high-performance and energy-efficient encryption/decryption engines on-die has become a reality in the sub-45nm CMOS era. Not only does this enable increased security of processor platforms, but also achieves unprecedented improvements in power-performance through the adoption of specialized hardware accelerator engines for various compute-intensive cryptography algorithms. In this presentation, we describe novel arithmetic and data-path technologies to enable highspeed on-die AES encryption/decryption accelerators for processor security, Secure Hashing Algorithm (SHA) compute engines, Galois-Field multipliers for public-key cryptography acceleration and secure on-die key generation using fully-digital random number generators based on metastable state elements. Circuit and design optimizations to enable ultra-low voltage operation of these accelerators are discussed to achieve up to a 10X higher energy-efficiency and a wide dynamic operating voltage range that enables scalable AES encryption/decryption down to sub-10mW per round, enabling power-efficient security to permeate into future mobile/hand-held/wearable devices.

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Additionally, circuit robustness against supply bounce is a key property that differentiates good level converter design. Novel flip-flops presented in this paper incorporate a half-latch level converter and a precharged level converter. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% flip-flop robustness improvement leading to 13% delay spread reduction in a CVS critical path. The proposed flip-flops also show 18% layout area reduction. Advantages of level conversion in a flip-flop over asynchronous level conversion in combinational logic are also discussed in terms of delay penalty and its sensitivity to supply bounce.

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Novel flip-flops presented in this paper incorporate a half-latch LC and a precharged LC. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% robustness improvement and 18% layout area reduction.