We present a new realizable reduced order modeling technique for RLC interconnect trees. Both lumped and distributed wire models can be used with this technique. Provable stability is achieved by using Hurwitz polynomials. Moment computation process is avoided but moments can still be matched implicitly. In experiments, the proposed Hurwitz three-pole model can accurately and efficiently capture inductive effect for both near end and far end nodes.

In high-performance chip design, the problem of net matching is often critical for achieving correct circuit performance. We adopt a conservative design, to route all matched nets with identical topologies and equal wire lengths to achieve zero skew. The problem is formulated as a variant of the D-dimensional Steiner tree problem. We propose a two-stage solution. The first stage uses an iterative improvement strategy to generate the Steiner tree topology for all the nets. The second stage places the nodes using one of two methods. The first approach expresses the optimal Steiner node positions as a linear programming solution, with average computational complexity O(n/sup 2/m/sup 2/), where n is the number of nets and m is the number of pins. Improved efficiency is achieved under the other approach by transforming the Manhattan metric to an l/sub /spl infin// norm using a 45/spl deg/ rotation of the solution space. The norm is then approximated by either an l/sub /spl lambda// norm, for suitably large values of /spl lambda/, or an exponential "penalty" function. The solution space in both approaches becomes strictly convex, allowing us to apply a greedy approach which converges to an optimal solution with great efficiency, leading to a dramatic speed-up versus the linear programming approach.

We address in this paper the fanout tree problem introduced by Berman, et. al., that is using buffer fanout trees to reduce the fanout delay in a technology mapped network. We construct two basic types of fanout trees and provide simple techniques to manipulate them for further delay reduction. These trees are inserted along critical paths throughout the network. We also perform gate-transformation, that is substitution of a gates of equivalent logical functions, if the technology permits. Experimental results show improvement over Touati's LT-tree construction technique.

Net matching is often critical for the correct performance of a circuit. We adopt a conservative design to route all matched nets with identical topology and equal wire lengths in order to achieve zero skew. We formulate the problem as one special D-dimensional Steiner tree problem. An iterative improvement strategy is used to generate the Steiner tree topology. We provide a more efficient method of computing the optimal Steiner point positions over the linear programming method involving a 45-degree rotation of the domain, and approximation matrices.