Demo Data from EDBT 2026 / reviewers in the wild / expert
Yuan C. Chou
dblp:28/6944
· DBLP profile ↗
4ranked-venue papers
4as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 70% Reconfigurable computing and FPGAs · 30% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › special-purpose processor › application-specific processor design
instruction path coprocessor |
0.1 | 2 | 2000 | PipeRench implementation of the instruction path coprocessor · MICRO 2000 Instruction path coprocessors · ISCA 2000 |
Reconfigurable computing and FPGAs
reconfigurable architecture |
0.0 | 1 | 2000 | PipeRench implementation of the instruction path coprocessor · MICRO 2000 |
Processor architecture and microarchitecture › instruction fetch
trace cache |
0.0 | 1 | 2000 | PipeRench implementation of the instruction path coprocessor · MICRO 2000 |
Methods — techniques the papers use, named apart from their topics
trace optimization · 0.0trace construction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Instruction path coprocessors
Yuan C. Chou, John Paul Shen |
ISCA | 1 |
| 2000 | PipeRench implementation of the instruction path coprocessorabstractThe paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-chip coprocessor that operates on the core processor's instructions to transform them into a new format that can be more efficiently executed. The I-COP can be used to implement many sophisticated hardware code modification techniques. We show how four specific techniques can be mapped to the PipeRench pipelined computation model. The experimental results show that a PipeRench I-COP used to perform trace construction and trace optimizations for a trace cache fill unit not only achieves good performance gains but can potentially be implemented in less than 10 mm/sup 2/ (assuming 0.18 micron technology) or approximately 3% of the die area of a current high-end microprocessor. We believe these results demonstrate the usefulness and feasibility of the I-COP concept. Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen |
MICRO | 1 |
| 1999 | Reducing branch misprediction penalties via dynamic control independence detectionabstractThis paper presents the concept of dynamic control independence (DCl) and shows how it can be detected and exploited in an out-of-order superscalar processor to reduce the performance penalties of branch mispredictions.We show how DCI can be leveraged during branch misprediction recovery to reduce the number of instructions squashed on a misprediction as well as how it can be used to avoid predicting unpredictable branches by fetching instructions out-of-order A realistic implementation is described and evaluated using six SPECint95 benchmarks.We show that exploiting DCI during branch misprediction recovety improves pe$ormance by 0.9-9.9% on a I-wide processol; by I&11.2% on an b-wide processor and by 1.9-15.3%on a 12-wideprocessol: We also show that using DCI information to fetch instructions out-of-order when an unpredictable branch is encountered potentially improves performance by 0.9-15.2% on a I-wide processol: by 2.0-14.8% on an 8-wide processor and by 2.6-16.2% on a 12wide processor: Some of the largest performance gains are observed on go and gee, which have traditionally posed the most d@cult challenge to aggressive branch prediction techniques.h-mission LO make digital or hard copies ol'all or par1 of this work for personal or classroom use is granrcd without fee provided that topics are not made or distributed for profit or commercial advantage and that copies bear this notice and lhe full citation on the tirst page.To copy otherwise, to republish, IO post on servers or to redistribute lo lisls.requires prior specific permission and/or a fee.ICS ")') Rhodes Greccc Yuan C. Chou, Jason Fung, John Paul Shen |
International Conference on Supercomputing | 1 |
| 1997 | A Realistic Study on Multithreaded Superscalar Processor Design
Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen |
Euro-Par | 1 |