Demo Data from EDBT 2026 / reviewers in the wild / expert
Lazaros Koromilas
dblp:28/7270
· DBLP profile ↗
9ranked-venue papers
3as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 4 · 1 first-authorSecurity and privacy · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
GPUs and heterogeneous computing · 64% Parallel and multicore computing · 24% Energy-efficient computing · 7% | |
| Computer networks
4 papers |
Software-defined and programmable networks · 56% Internet architecture and protocols · 25% Datacenter networks · 19% | |
| Network and information security
1 paper |
Network security · 100% |
Topics — the 8 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing › GPU computing › GPGPU acceleration
GPU-accelerated network processing |
0.5 | 2 | 2017 | Design and Implementation of a Stateful Network Packet Processing Framework for GPUs · IEEE/ACM Trans. Netw. 2017 GASPP: A GPU-Accelerated Stateful Packet Processing Framework · USENIX ATC 2014 |
Software-defined and programmable networks
programmable data plane |
0.4 | 3 | 2017 | Enabling End-Host Network Functions · SIGCOMM 2015 Design and Implementation of a Stateful Network Packet Processing Framework for GPUs · IEEE/ACM Trans. Netw. 2017 GASPP: A GPU-Accelerated Stateful Packet Processing Framework · USENIX ATC 2014 |
Internet architecture and protocols
packet processing |
0.3 | 1 | 2017 | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures · IEEE/ACM Trans. Netw. 2017 |
Software-defined and programmable networks › programmable data plane
software packet processing |
0.3 | 1 | 2017 | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures · IEEE/ACM Trans. Netw. 2017 |
Network security › intrusion detection and prevention
intrusion detection |
0.3 | 1 | 2017 | Design and Implementation of a Stateful Network Packet Processing Framework for GPUs · IEEE/ACM Trans. Netw. 2017 |
Parallel and multicore computing › parallel scheduling
adaptive scheduling |
0.3 | 1 | 2017 | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures · IEEE/ACM Trans. Netw. 2017 |
GPUs and heterogeneous computing
heterogeneous architecture |
0.3 | 1 | 2017 | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures · IEEE/ACM Trans. Netw. 2017 |
Energy-efficient computing
power management |
0.1 | 1 | 2017 | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures · IEEE/ACM Trans. Netw. 2017 |
Methods — techniques the papers use, named apart from their topics
flow tracking · 0.9TCP stream reassembly · 0.9SIMT thread management · 0.9scheduling · 0.6measurement · 0.6programmable NIC · 0.4kernel bypass · 0.4GPU acceleration · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | OTTer: A Scalable High-Resolution Encrypted Traffic Identification Engine
Eva Papadogiannaki, Constantinos Halevidis, Periklis Akritidis, Lazaros Koromilas |
RAID | 4 |
| 2017 | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware ArchitecturesabstractHeterogeneous and asymmetric computing systems are composed by a set of different processing units, each with its own unique performance and energy characteristics. Still, the majority of current network packet processing frameworks targets only a single device (the CPU or some accelerator), leaving the rest processing resources unused and idle. In this paper, we propose an adaptive scheduling approach that supports the heterogeneous and asymmetric hardware, tailored for network packet processing applications. Our scheduler is able to respond quickly to dynamic performance fluctuations that occur at real time, such as traffic bursts, application overloads, and system changes. The experimental results show that our system is able to match the peak throughput of a diverse set of packet processing applications, while consuming up to $3.5\times$ less energy. Eva Papadogiannaki, Lazaros Koromilas, Giorgos Vasiliadis, Sotiris Ioannidis |
IEEE/ACM Trans. Netw. | 2 |
| 2017 | Design and Implementation of a Stateful Network Packet Processing Framework for GPUsabstractGraphics processing units (GPUs) are a powerful platform for building the high-speed network traffic processing applications using low-cost hardware. The existing systems tap the massively parallel architecture of GPUs to speed up certain computationally intensive tasks, such as cryptographic operations and pattern matching. However, they still suffer from significant overheads due to critical-path operations that are still being carried out on the CPU, and redundant inter-device data transfers. In this paper, we present GASPP, a programmable network traffic processing framework tailored to modern graphics processors. GASPP integrates optimized GPU-based implementations of a broad range of operations commonly used in the network traffic processing applications, including the first purely GPU-based implementation of network flow tracking and TCP stream reassembly. GASPP also employs novel mechanisms for tackling the control flow irregularities across SIMT threads, and for sharing the memory context between the network interfaces and the GPU. Our evaluation shows that GASPP can achieve multigigabit traffic forwarding rates even for complex and computationally intensive network operations, such as stateful traffic classification, intrusion detection, and packet encryption. Especially when consolidating multiple network applications on the same system, GASPP achieves up to 16.2× speedup compared with different monolithic GPU-based implementations of the same applications. Giorgos Vasiliadis, Lazaros Koromilas, Michalis Polychronakis, Sotiris Ioannidis |
IEEE/ACM Trans. Netw. | 2 |
| 2016 | GRIM: Leveraging GPUs for Kernel Integrity Monitoring
Lazaros Koromilas, Giorgos Vasiliadis, Elias Athanasopoulos, Sotiris Ioannidis |
RAID | 1 |
| 2015 | Enabling End-Host Network FunctionsabstractMany network functions executed in modern datacenters, e.g., load balancing, application-level QoS, and congestion control, exhibit three common properties at the data-plane: they need to access and modify state, to perform computations, and to access application semantics -- this is critical since many network functions are best expressed in terms of application-level messages. In this paper, we argue that the end hosts are a natural enforcement point for these functions and we present Eden, an architecture for implementing network functions at datacenter end hosts with minimal network support. Eden comprises three components, a centralized controller, an enclave at each end host, and Eden-compliant applications called stages. To implement network functions, the controller configures stages to classify their data into messages and the enclaves to apply action functions based on a packet's class. Our Eden prototype includes enclaves implemented both in the OS kernel and on programmable NICs. Through case studies, we show how application-level classification and the ability to run actual programs on the data-path allows Eden to efficiently support a broad range of network functions at the network's edge. Hitesh Ballani, Paolo Costa, Christos Gkantsidis, Matthew P. Grosvenor, Thomas Karagiannis, Lazaros Koromilas, Greg O'Shea |
SIGCOMM | 6 |
| 2014 | Efficient software packet processing on heterogeneous and asymmetric hardware architecturesabstractHeterogeneous and asymmetric computing systems are composed by a set of different processing units, each with its own unique performance and energy characteristics. Still, the majority of current network packet processing frameworks targets only a single device (the CPU or some accelerator), leaving other processing resources idle. In this paper, we propose an adaptive scheduling approach that supports heterogeneous and asymmetric hardware, tailored for network packet processing applications. Our scheduler is able to respond quickly to dynamic performance fluctuations that occur at real-time, such as traffic bursts, application overloads and system changes. The experimental results show that our system is able to match the peak throughput of a diverse set of packet processing workloads, while consuming up to 3.5x less energy. Lazaros Koromilas, Giorgos Vasiliadis, Ioannis Manousakis, Sotiris Ioannidis |
ANCS | 1 |
| 2014 | Flying Memcache: Lessons Learned from Different Acceleration StrategiesabstractDistributed key-value and always-in-memory store is employed by large and demanding services, such as Facebook and Amazon. It is apparent that generic implementations of such caches can not meet the needs of every application, therefore further research for optimizing or speeding up cache operations is required. In this paper, we present an incremental optimization strategy for accelerating the most popular key-value store, namely memcached. First we accelerate the computational unit by utilizing commodity GPUs, which offer a significant performance increase on the CPU-bound part of memcached, but only moderate performance increase under intensive I/O. We then proceed to improve I/O performance by replacing TCP with a fast UDP implementation in user-space. Putting it all together, GPUs for computational operations instead of CPUs, and UDP for communication instead of TCP, we are able to experimentally achieve 20 Gbps line-rate, which significantly outperforms the original implementation of memcached. Dimitris Deyannis, Lazaros Koromilas, Giorgos Vasiliadis, Elias Athanasopoulos, Sotiris Ioannidis |
SBAC-PAD | 2 |
| 2014 | GASPP: A GPU-Accelerated Stateful Packet Processing Framework
Giorgos Vasiliadis, Lazaros Koromilas, Michalis Polychronakis, Sotiris Ioannidis |
USENIX ATC | 2 |
| 2011 | CassMail: A Scalable, Highly-Available, and Rapidly-Prototyped E-Mail Service
Lazaros Koromilas, Kostas Magoutis |
DAIS | 1 |