High-frequency variation of the common-mode voltage (CMV) causes severe leakage current and electromagnetic interference (EMI) in photovoltaic (PV) generation and motor drive systems. This paper proposes a discontinuous PWM (DPWM) to reduce CMV for three-phase three-level inverters under different NP voltage conditions. Firstly, the relationship between the CMV and NP voltage is revealed. Then, the switching-state sequence is optimized to reduce the magnitude and frequency variations of the CMV. Furthermore, since the switching state of one phase is clamped at each switching cycle, the switching loss is also reduced. Finally, a 6-kW inverter prototype is built, and experimental results show that the proposed scheme features lower CMV, lower leakage current, and higher efficiency.

Hysteresis current control is considered an effective method to achieve full power range zero-voltage-switching (ZVS) operation and good gird current quality of the critical mode (CRM) LCL-type grid-tied inverter. However, with the large-scale grid connection of distributed power generation systems (DPGS), the control performance of the LCL-type grid-tied inverter is seriously challenged by the large number of harmonics contained in the point of common coupling (PCC). In this paper, by combining the physical interpretation of the full grid voltage feedforward (GVF) and the physical model of the hysteresis current control (HCC) CRM LCL-type grid-tied inverter, a full GVF scheme is proposed for improving the grid current THD of the single-phase HCC-CRM LCL-type grid-tied inverter. All harmonics caused by the distorted grid voltage can be significantly suppressed by feeding forward the derivative term of the grid voltage to the hysteresis-band reference. A 1-kW single-phase LCL-type grid-tied inverter is built, and experiments are conducted to verify the effectiveness of the proposed strategy.

Neutral-point (NP) voltage imbalance causes severe alternating output current distortion in three-phase three-level inverters when conventional discontinuous PWM (DPWM) schemes are employed. Existing improved DPWM schemes can not achieve low total harmonic distortion (THD) and simple digital implementation simultaneously. In this paper, a pulse-width compensation (PWC) scheme is proposed to improve the THD performance of DPWM-based three-level inverters under unbalanced NP voltage conditions. By using the proposed PWC scheme, the pulse width of the bridge-leg voltage of the unclamped phases is compensated according to the NP voltage. As a result, the fundamental component of the bridge-leg voltage is not affected by the NP voltage, and the alternating output current distortion is improved. Finally, a 6-kW inverter prototype is built, and experimental results show that the proposed PWC scheme can achieve low THD and simpler digital implementation than the existing improved DPWM scheme.