Deploying high-performance Deep Neural Networks (DNNs) on embedded hardware platforms, such as FPGAs, not only promises low latency and high energy-efficiency implementations, but also poses significant challenges due to the resource constraints of such systems. Recent efforts have focused on approximation techniques at the algorithmic level of DNNs to reduce resource requirements, such as network pruning and quantization of weights and activations. Other approximation techniques that approximate register transfer level (RTL) designs by substituting single components with approximated ones are not yet applied to DNNs, mainly because these techniques do not scale well to the typically huge RTL representations of DNNs.This paper introduces the idea of a two-stage approximation methodology for DNNs that combines algorithmic level with RTL approximation to achieve reduced resource requirements at acceptable accuracy. As a novel instance of that idea, we leverage the LogicNets approach that performs a low-bit quantization to map DNN neurons to LUT representations and the CIRCA framework that provides a search-based approximation flow for RTL designs. To balance hardware efficiency and accuracy, and to achieve acceptable runtimes, we limit the RTL approximation to a subset of neurons identified as resilient using a systematic sampling approach. Experimental results demonstrate the potential of the methodology with up to 15.20% further decrease in resource utilization with a mere 2.15% accuracy drop.

To overcome the bottleneck of the classical processor-centric architectures, Computation-in-Memory (CiM) is a promising paradigm where operations are performed directly in memory. Recent works propose the use of CiM to accelerate neural networks or hyperdimensional computing, but also for memory encryption solutions. As CiM facilitates the computation in the analog domain and the output is driven through current sensing, CiM could potentially be highly vulnerable to power side-channel attacks. In this work, we analyze the vulnerability for power side-channel attacks in various CiM implementations based on Static Random Access Memory (SRAM) and emerging nonvolatile memristive technologies. Our results show that a side-channel attacker can recover secret data used in an XOR operation with only a few hundred measurements, where CiM architectures based on emerging memristive technologies are more vulnerable than SRAM-based CiM. Therefore, we propose two different types of countermeasures based on hiding and masking, which are tailored to CiM architectures. The efficiency of our proposed countermeasures is shown by both attacks and leakage assessment methodologies using one million measurement traces.

Memristive devices offer energy and area efficient non-volatile data storage for data-intense Ternary Content Ad-dressable Memory (TCAM) architectures. However, depending on the storage implementation in the bitcell design, the matching functionality shows multiple undesired discharge effects leading to false look-up results. In particular, the ternary storage suffers during the look-up operation from a poor resistance ratio, match-line leakage and device variabilities. In this paper, we investigate the inherent, design-dependent limitations in the ternary state storage capability due to different memristive TCAM bitcell design parameters and device variabilities. We test these limits based on variability-aware device simulations and isolate crucial parameters for the optimization of memristive TCAMs.

Analog Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency. Spin-Transfer Torque Magnetic Memory (STT-MRAM) is one of the promising technologies for CiM architectures. Although STT-MRAM has various benefits, it does not have the potential to be used directly in analog multi-value CiM operations due to its limited levels of cell resistance states. In this paper, we propose a novel flexible multi-value design for STT-MRAM (MVSTT) with the potential to be used for multi-value CiM. In the multi-value CiM, we are able to have various 2sresistive state combinations from$s$selected MTJs, which is not possible in the normal STT-MRAM CiM. The size of the MVSTT can be adjusted at run-time depending on the application's requirements. The benefits of the proposed scheme are quantified in representative applications such as multi-value matrix multiplications, which is the basic computation of Neural Networks applications. For the multi-value matrix multiplication, the energy, and delay gain is up to 9.7 × and 13.3 ×, respectively, to non-CiM matrix-vector-multiplication. Also, for the neural network, the proposed design allows up to a 32 × reduction in the STT-MRAM cells per crossbar to achieve a similar inference accuracy as the binarized neural network.

Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency, which is a promising approach to address so-called memory wall of conventional von Neumann architectures. Redox-based Random access memory (ReRAM) is an appropriate candidate for the realization of CiM concepts in CMOS co-integrated crossbar structures. However, ReRAM devices suffer from inherent variability in fabrication and operation. In this paper, we propose a statistical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on this, a comprehensive reliability analysis is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture has a high failure probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

Emerging non-volatile memories facilitate the Computation in Memory (CiM) paradigm. Performing operations with the concept of CiM plays a crucial role in the efficiency improvement of data-intensive applications. Resistive switching RAM (ReRAM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) are promising candidates for the CiM implementation. Reliable CiM implementation with these resistive non-volatile memories (memristive devices) is challenging and error-prone since the manufacturing process of both the memristive components and the CMOS components are susceptible to the temperature- and voltage-dependent variation. Moreover, the small distance between the distinct resistive levels of the STT-MRAM, and time-dependent resistance drift in ReRAM, exacerbates the reliability of CiM implementations. In this paper, we perform a detailed study on the impact of the temperature and voltage biasing on the variation in both the STT-MRAM and ReRAM technologies as well as propose a voltage tuning scheme to significantly improve the sensing reliability of CiM implementations based on these technologies. We also investigate the impact of our proposed voltage tuning scheme on the power consumption and performance of the CiM circuitry.