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Bhakta K. Roy

dblp:281/3205 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1974
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault diagnosis
0.011974
Diagnosis and Fault Equivalence in Combinational Circuits · IEEE Trans. Computers 1974
Electronic design automation › hardware verification and test › fault modeling
fault equivalence
0.011974
Diagnosis and Fault Equivalence in Combinational Circuits · IEEE Trans. Computers 1974
Electronic design automation
hardware verification and test
0.011974
Diagnosis and Fault Equivalence in Combinational Circuits · IEEE Trans. Computers 1974

Methods — techniques the papers use, named apart from their topics

gate sensitivity analysis · 0.0diagnostic table · 0.0
YearPublicationVenuePosition
1974 Diagnosis and Fault Equivalence in Combinational Circuits
abstract
Two procedures are presented: one for diagnosis of single-gate failures and the other for deriving equivalence classes of single faults. Both procedures require use of a diagnostic table which lists gate sensitivities and primary output values for all input patterns in a set of tests which contains at most U tests, where U is an upper bound derived in the text. A gate is defined to be an n-input single-output combinational circuit (n ≥ 1) and a failure is any detectable transformation of the correct gate function. The information contained in a diagnostic table can be used to locate a faulty gate and describe its failed function. Equivalence classes are derived from a diagnostic table by first specifying the primary output values in accordance with a theorem given in the text and then deriving the corresponding gate functions. Examples are given to illustrate both the procedures.
Bhakta K. Roy
IEEE Trans. Computers1