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Sven Gregorio

dblp:281/8245 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory controller
DRAM scheduling
0.512021
SIMDRAM: a framework for bit-serial SIMD processing using DRAM · ASPLOS 2021
Memory systems
processing-in-memory
0.512021
SIMDRAM: a framework for bit-serial SIMD processing using DRAM · ASPLOS 2021
Memory systems › processing-in-memory
processing-using-DRAM
0.512021
SIMDRAM: a framework for bit-serial SIMD processing using DRAM · ASPLOS 2021
Processor architecture and microarchitecture
SIMD
0.112021
SIMDRAM: a framework for bit-serial SIMD processing using DRAM · ASPLOS 2021

Methods — techniques the papers use, named apart from their topics

bit-serial SIMD · 0.5MAJ/NOT representation · 0.5
YearPublicationVenuePosition
2021 SIMDRAM: a framework for bit-serial SIMD processing using DRAM
abstract
Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable full adoption of processing-using-DRAM, it is necessary to provide support for more complex operations. In this paper, we propose SIMDRAM, a flexible general-purpose processing-using-DRAM framework that (1) enables the efficient implementation of complex operations, and (2) provides a flexible mechanism tosupport the implementation of arbitrary user-defined operations. The SIMDRAM framework comprises three key steps. The first step builds an efficient MAJ/NOT representation of a given desired operation. The second step allocates DRAM rows that are reserved for computation to the operation’s input and output operands, and generates the required sequence of DRAM commands to perform the MAJ/NOT implementation of the desired operation in DRAM. The third step uses the SIMDRAM control unit located inside the memory controller to manage the computation of the operation from start to end, by executing the DRAM commands generated in the second step of the framework. We design the hardware and ISA support for SIMDRAM framework to (1) address key system integration challenges, and (2) allow programmers to employ new SIMDRAM operations without hardware changes.
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, João Dinis Ferreira, Nika Mansouri-Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gómez-Luna, Onur Mutlu
ASPLOS3