The semiconductor industry is pivotal to Europe's economy, especially within the industrial and automotive sectors. However, Europe faces a significant shortfall in chip design capabilities, marked by a severe skilled labor shortage and lagging contributions in the design value chain segment. This paper explores the role of European universities and academic initiatives in enhancing chip design education and research to address these deficits. We provide a comprehensive overview of current European chip design initiatives, analyze major challenges in recruitment, productivity, technology access, and design enablement, and identify strategic opportunities to strengthen chip design capabilities within academic institutions. Our analysis leads to a series of recommendations that highlight the need for coordinated efforts and strategic investments to overcome these challenges.

Edge Artificial Intelligence (AI) relies on the integration of Machine Learning (ML) into even the smallest embedded devices, thus enabling local intelligence in real-world applications, e.g. for image or speech processing. Traditional Edge AI frameworks lack important aspects required to keep up with recent and upcoming ML innovations. These aspects include low flexibility concerning the target hardware and limited support for custom hardware accelerator integration. Artificial Intelligence for Embedded Systems Framework (AIfES) has the goal to overcome these challenges faced by traditional edge AI frameworks. In this paper, we give a detailed overview of the architecture of AIfES and the applied design principles. Finally, we compare AIfES with TensorFlow Lite for Microcontrollers (TFLM) on an ARM Cortex-M4-based System-on-Chip (SoC) using fully connected neural networks (FCNNs) and convolutional neural networks (CNNs). AIfES outperforms TFLM in both execution time and memory consumption for the FCNNs. Additionally, using AIfES reduces memory consumption by up to 54% when using CNNs. Furthermore, we show the performance of AIfES during the training of FCNN as well as CNN and demonstrate the feasibility of training a CNN on a resource-constrained device with a memory usage of slightly more than 100 kB of RAM.

The emerging Edge Artificial Intelligence (AI) paradigm is a key driver of innovation in many areas such as audio or industrial sensor data processing. Edge AI relies on the integration of machine and deep learning-based signal processing into even the smallest embedded devices thus enabling local intelligence in real-world applications. Nevertheless, classical signal processing techniques such as the Fast Fourier Transform (FFT) still remain an essential component of Edge AI systems, especially in the context of data preprocessing. However, their optimization with respect to resource requirements is often neglected although it can increase the performance of the overall system. In this paper, we present a new approximate FFT (AFFT) approach that enables the end-to-end resource optimization of digital signal processing (DSP) pipelines in Edge AI systems. The approach combines an aggressive FFT parameter quantization with error mitigation techniques to trade off accuracy and performance. To evaluate the methodology, a flexible code generation framework is implemented. We analyze the accuracy of the AFFT, demonstrate its capabilities in an audio classification use-case involving a convolutional neural network (CNN) and benchmark the approach on an ARM Cortex-M4-based System-on-Chip (SoC). Our methodology maintains the classification accuracy of the CNN close to the full-precision level while outperforming the ARM CMSIS FFT both in execution time and energy consumption.