This paper introduces a dynamic current comparator employing a parasitic charge recycling technique to achieve an ultra-low energy per comparison of 175 fJ. Furthermore, incorporating a switched capacitor supply in the static portion of the circuit, the comparison energy is further reduced to 55 fJ, more than three times lower. The proposed circuit, designed and extensively simulated in a 130-nm CMOS process with thick gate MOS transistors, demonstrates a comparison time of 3.8 ns, with a 100-nA input difference and a 32-MHz clock, while offering an input-referred noise of 2.9 nArms. These features make the proposed comparator highly suitable for medium-to high-resolution data conversion systems, particularly in biomedical and sensor-readout applications. Additionally, it is well-suited for high-speed and cryogenic CMOS systems, where current-mode architectures are becoming increasingly relevant.

A 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm CMOS is presented. Designed for the readout of inertial sensors in micro-electromechanical systems (MEMS) technology, it combines an asynchronous control scheme with a 2-bit per cycle architecture achieving enhanced energy efficiency. Operating at a 1-MS/s sampling rate, the proposed ADC draws 8.9-µA of total current from a 1.8-V supply. Additionally, it demonstrates an SNDR of 63.2 dB across the entire Nyquist bandwidth, resulting in a Walden figure-of-merit (FoM) of 13.6 fJ/conv-step. The achieved energy efficiency makes the proposed ADC suitable for battery-powered applications requiring medium resolution and data rate.

This paper proposes a three-stage operational transconductance amplifier (OTA) with slew-rate enhancing, especially designed for interfacing triboelectric nanogenerator sensors in smart textile applications. The proposed OTA, designed in a 130-nm BCD process, features 0.015-mm2area and 2.7-µW power consumption with 1.3-V supply voltage, while meeting the specifications of the targeted application, thus constituting a very compact low-power low-voltage solution. The proposed OTA was extensively simulated with Cadence Virtuoso, verifying its post-layout performance and robustness against process, voltage and temperature (PVT) variations.

This paper presents a monolithic GaN current sense circuit designed for the high-side of a 100-V half-bridge. The circuit is engineered to minimize current offsets and response times across a wide range of input voltages (10 V to 100 V), as well as varying temperatures and current loads. It is capable of tracking inductor current ripples and detecting the zero-current condition of the half-bridge high-side power transistor. The proposed solution demonstrates a simulated loop gain exceeding 100 dB and a bandwidth of 43.9 MHz, which achieves an accuracy of 99.4% and a response time of 145 ns under operating conditions of 50-V input voltage, 10-A current load, and 27°C.

This work presents the design of a bipolar junction transistor (BJT)-based temperature sensor with a sigma-delta analog-to-digital converter ($\Sigma \Delta $ADC) fabricated in a 0.6$\mu $m BiCMOS process. The sensor utilizes a proportional to absolute temperature (PTAT) current source embedding an auto-zeroing amplifier to bias the BJT core while effectively reducing offset errors. Additionally, this work achieves the combination of the temperature-sensing BJT core and the$\Sigma \Delta $modulator, utilizing dynamic element matching (DEM) technique to accurately generate three different ratios (1:9, 9:1, 5:5) of BJT bias currents to cooperate with the modulator for modulation. The innovative modulation method in this work can reduce the errors caused by the operational amplifier offset voltage and BJT mismatch, completing the digitization of temperature without the need for a reference voltage source. Moreover, the sensor integrates a complete digital signal processor (DSP), allowing on-chip calibration by adjusting the operating cycle of the modulator and the initial value of the counter to obtain accurate and directly readable temperature data. It operates under a 3.3 V supply within a temperature range from −50 °C to 125 °C. Lastly, it achieves a 17 mK resolution and an inaccuracy of ±1.5 °C (3$\sigma $) after an on-chip single-point calibration.

This paper focuses on the impact of segmentation on the linearity performance of gigasample rate current-steering digital-to-analog converters (DACs). The effect of their output impedance drop and code-dependency occurring at increasingly higher data rates is studied with the purpose of deriving relevant design constraints about the segmentation scheme choice. This analysis is supported by extensive simulation results carried out with special attention to the spurious-free-dynamic-range (SFDR) and third-order-intermodulation-distortion (IM3) metrics. Lastly, a 10-bit 6.4 GS/s DAC designed in a 55-nm BiCMOS technology is presented and discussed in relation to the previously determined scenarios. Besides featuring a 65.9-dBc SFDR at 1 GHz and an IM32.

This paper presents a SAR-assisted first order incremental$\Sigma\Delta$analog-to-digital converter (ADC) equipped with an accumulation based sample and hold (S/H) circuit to effectively limit its kT/C noise contribution, potential bottleneck for the resolution performance of the converter. This system has been designed for shunt current measurements in the electrical drives battery management framework; the sensed and digitized current information is needed for a proper monitoring and regulation of the behaviour of these essential devices for automotive applications. The converter has been developed at the behavioural level in the MATLAB Simulink environment with special attention to the S/H circuit which has been analyzed in Cadence Virtuoso; the complete system features a high common mode voltage (HCMV) in the order of tens of Volts, a peak-to-peak 50 mV differential input range and a target resolution of 12 bits.

This paper presents a trimming technique to suppress the thermal effects of process spread of BJT-based temperature processing circuits. The proposed calibration method has the advantage of requiring a reading at a single temperature while compensating for the spread of the thermal behaviour of the base-to-emitter voltage of bipolar transistors; in addition to this, the effectiveness of the proposed technique is improved by an exponential approach carried out on the design of the trimming structure. The strength of the presented technique is shown to be effective on a 6-bit trimming circuit designed and extensively simulated in a standard 180-nm CMOS process; this implementation provides a reduction of the considered spread of about 90% making it suitable for a number of applications in which process variations limit the accuracy of the circuit.