In recent years, Approximate Computing has been gaining space as a technique for tackling energy requirements in error-resilient applications, while the usage of Machine Learning systems has steadily increased. This work explores two different approaches for approximation in comparator circuits and their impact on Decision Tree applications, observing power and accuracy metrics. Two gate-level architectures are proposed for dedicated comparators, approximating 25% or 50% of least significant bits using different techniques. The circuits were described in 7 nm FinFET technology. The approximate comparators were then evaluated in a Decision Tree classification model using five continuous and mixed attribute datasets. The 25% LSB approximate comparator proposed improves the energy efficiency in Decision Tree applications, reducing from 12% up to 84% the power per inference while presenting minor deviations in accuracy compared to the exact baseline.

The increasing use of Machine Learning applications has caused a high demand for design techniques targeting the trade-off between energy consumption and accuracy in inference models. In this scenario, Decision Trees are models widely used in embedded systems and Internet of Things applications. They are less resource intensive than Neural Networks, and maintain acceptable accuracy results for various problems. This project proposes a framework for evaluating the improvement of the power-accuracy trade-off in decision tree models using approximate circuits. The results of the electrical evaluation and accuracy provided in each step are obtained by applying different approximation and quantization techniques. This information can be used together with power-accuracy metrics to find the best comparator circuits for different applications of Decision Trees and dedicated hardware requirements.

The Gaussian image filter is a compute-intensive approach to reduce undesirable artifacts and generally serves as a pre-processing technique for emerging applications related to visual computing systems. This work evaluates alternatives for the design of power-efficient Gaussian Filters. The proposed optimization strategy combines: 1) a refactored function to minimize the arithmetic operations, and 2) a design space exploration investigating different approximation scenarios applied to the full adders. The exact version of our refactored Gaussian Filter architecture reduces the total power consumption and the circuit area by 18% and 12%, respectively compared with the baseline Gaussian Filter architecture. Moreover, the combination of different approximation levels with the refactored architecture provides design options with power reductions from 21% to 59% compared with the baseline Gaussian Filter architecture.