EDBT 2026 Demo / reviewers in the wild / expert
Zhengguang Tang
dblp:282/6724
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2026
0000-0002-5236-9745ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Accurate Analytic Equation Generation for Compact Modeling with Physics-Assisted Kolmogorov-Arnold NetworksabstractThis article proposes a method to generate accurate and concise analytic equations for device compact modeling using Physics-Assisted Kolmogorov–Arnold Networks (PKAN). The equations are directly extracted from the trained neural network architecture. PKAN uses variable activation functions informed by prior physical knowledge to model device behaviors. Similarity constraints map these trained activation functions to mathematical symbols. Sparsification techniques simplify the network structure, producing concise and explicit equations. This article also presents four approaches for physics-assisted device modeling using PKAN: (1) generating entire continuous equations without human intervention, (2) applying correlation factors to existing models without requiring knowledge of internal physical mechanisms, (3) revising specific parts of existing models, and (4) automatically extending existing models. Experimental results show that PKAN demonstrates significant accuracy improvements, achieving error reductions of 91.8%, 91.5%, 66.2%, and 83.7% for corresponding experiments, respectively. These findings demonstrate PKAN’s potential for various device modeling applications. By combining the precision of neural networks with the clarity of symbolic representation, PKAN offers a powerful tool for device modeling applications. Zhengguang Tang, Zhenhai Cui, Cong Li 0023, Handing Wang, Hailong You |
ACM Trans. Design Autom. Electr. Syst. | 2 |
| 2023 | ASSURER: A PPA-friendly Security Closure Framework for Physical DesignabstractHardware security is emerging in the very large scale integration (VLSI). The seminal threats, like hardware Trojan insertion, probing attacks, and fault injection, are hard to detect and almost impossible to fix at post-design stage. The optimal solution is to prevent them at the physical design stage. Usually, defending against them may cause a lot of power, performance, and area (PPA) loss. In this paper, we propose a PPA-friendly physical layout security closure framework ASSURER. Reward-directed placement refinement and multi-threshold partition algorithm are proposed to assure Trojan threats are empty. Cleaning up probing attacks is established on a patch-based ECO routing flow. Evaluated on the ISPD'22 benchmarks, ASSURER can clean out the Trojan threat with no leakage power increase when shrinking the physical layout area. When not shrinking, ASSURER only increases 14% total power. Compared with the work of first place in the ISPD2022 Contest, ASSURE reduced 53% additional total power consumption, and probing vulnerability can be reduced by 97.6% under the premise of timing closure. We believe this work shall open up a new perspective for preventing Trojan insertion and probing attacks. Hailong You, Zhengguang Tang, Benzheng Li, Cong Li 0023, Xiaojue Zhang |
ASP-DAC | 3 |
| 2022 | High quality hypergraph partitioning for logic emulation
Benzheng Li, Zhongdong Qi, Zhengguang Tang, Xiyi He, Hailong You |
Integr. | 3 |