Diagnosis simulation based on stuck-at faults cannot expose all chain diagnosis problems because silicon defects don’t behave exactly as stuck-at faults. For chain failures, the fault effect can be activated during scan shift cycles and capture cycles in scan test patterns. The activation conditions of silicon defects are generally more complex and do not activate the fault effect in all cycles. To accurately estimate diagnosis coverage during chain diagnosis simulation, this paper proposes using distinguishing bits. Distinguishing bits, which are simulation-failing bits of one fault but not simulation-failing bits of another fault, are used in this paper to distinguish each silicon defect from others. The chain diagnosis quality of silicon defects can be improved by increasing the distinguishing bits of all scan cell faults. Specific diagnosis test patterns are proposed to increase the number of distinguishing bits of each fault. If the diagnosis test patterns cannot be created, adaptive diagnosis points are proposed to modify the designs to facilitate the creation of these diagnosis test patterns.

Diagnosis of defects on scan chains is the established methodology for improving semiconductor manufacturing yield throughout the production cycle. The best possible result is to obtain a perfect diagnosis resolution, i.e. identifying a single scan cell per defect. With increased structural complexity and emergence of new production technologies, like backside power, there is a need to improve diagnosis callout beyond single-cell to include transistor-level visibility. In this paper we will present a novel end-to-end software-based methodology for enhancing scan chain diagnosis resolution with cell aware information. The new diagnosis methodology enables the isolation of defects in control signals local to multi-bit register arrays. Volume diagnosis benchmarks and silicon data will be shown to present suspect area improvements that will allow for faster physical failure analysis (PFA) turnaround times.

A pre-silicon design-for-diagnosis flow is a critical step in IC manufacturing. It is the key to achieving high diagnosis quality, which is necessary to improve yield and meet time-to-volume business requirements. This paper introduces a novel mechanism that significantly enhances this process. By inserting an XOR gate at scan cells, we enable these cells to operate in an additional mode, thereby improving their diagnosability. The activation of this extra mode is facilitated by a combination of a diagnosis-enable signal bit and the scan-enable signal. A key aspect of our approach is using a local scan cell without an additional input pin to provide the diagnosis-enable signal, a practical innovation that enhances the efficiency of the manufacturing process.

Diagnosis becomes a much more prevalent factor in the successful fabrication process of a design. In order to keep up with continuously shrinking technology nodes, compression along with compaction techniques became a standard methodology allowing to control the cost of test. Typically compaction techniques focus on detectability thus maintaining high quality of test, but neglect or, in many cases, ignore their impact on diagnosis. This paper presents a compactor which allows significantly improving chain diagnosis resolution while maintaining high quality standards from detectability point of view and having virtually no impact on test time and logic diagnosis. The paper presents the X-press compactor which is driven in a way allowing to maximize diagnostic ability of chain failures. Specifically, the number of physical failure analysis-ready cases increased up to two times. The feasibility and efficiency of the proposed solution is confirmed by a number of experimental results performed for industrial designs, including actual chain diagnosis.