Gaku Ogihara

dblp:282/9024 · DBLP profile ↗
← Back
5ranked-venue papers
1as first author
4since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author · 4 since 2021
YearPublicationVenuePosition
2022 High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST
abstract
This paper demonstrates that a 20-bit subrange ADC for high precision voltage measurement can be implemented with standard ATE resource and BOST circuits, without special devices. Our prototype 20-bit ADC employs subranging architecture and consists of a 16bit ADC (LTC1867), a 20-bit DAC (ADC5791), Arduino and some additional circuits. Its operation has been confirmed with simulations and experiments, and effects of non-idealities for each circuit to the overall 20-bit ADC performance have been evaluated. We consider that a 16bit audio-band digitizer in an ATE system can be used as the 16bit ADC while the 20-bit DAC as well as an error amplifier (another component for the subranging ADC) can be implemented with BOST circuits.
Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001
ATS5
2022 Innovative Practices Track: Innovative Analog Circuit Testing Technologies
abstract
Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.
Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragan Asian, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Jiang-Lin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi 0001, Keno Sato, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa
VTS8
2021 High Precision Measurement of Sub-Nano Ampere Current in ATE Environment
abstract
Background: In IoT system devices, currents become smaller and they have to operate for ten years with a coin cell battery. Then their accurate and fast measurement is required at the mass production shipping stage. However, the conventional method needs a large resistor (Rm, MΩ-order in Fig. 1) which makes the testing slow, and the ATE environment is noisy.Research Target: Our target is the development of a testing technique to measure the current in the order of nano or sub-nano ampere with high linearity in the noisy ATE environment and in short time as well as with only additional low cost built-out self-test (BOST) circuits.Approach: Fig. 2 shows the proposed current measurement circuits. The current under test is converted to the voltage through an op-amp and a resistor Rmof 10kΩ, and it is then converted to the AC voltage; these conversions are done with small BOST circuits. The AC voltage is amplified and converted to the digital signal through an AC amp, a sample/hold circuit and an ADC. FFT is performed and its power spectrum is calculated; the input current value is obtained. The resistor (Rm) of 10k generates spike noises which are spurious components in the power spectrum. However, usage of the sample/hold circuit reduces their effects. Thanks to the DC-AC conversion, the measurement accuracy is not degraded by the system noise in the low frequency region. The nano-ampere current and the resistor of 10kΩ produces several tens μV level voltage and our previous research in [1, 2] shows that the DC-AC conversion method can measure this level of the voltage accurately and in short time. Also, its multi-channel measurement is possible.Experiment Verification: Preliminary experiment with the prototype system in Fig. 2 was performed and its measured result is shown in Fig. 3. The measurement circuit gain in Fig. 2 was calibrated with 1.0nA input current (Iin), which corresponds to Vin of 10.0μV. Also an offset of 0.2μV due to electromotive force (EMF) was calibrated. We see in Fig. 3 that the proposed method can measure the current as low as 50pA. So far EMF limits the lowest measurable current. Fig. 4 shows 100 times of measurements for 1.0nA without averaging. Each measured current value is obtained by 1K-point FFT with 25.6 ksps, 16-bit ADC (myDAQ) usage and the measurement time of 40ms. The measured data is within 0.94nA to 1.07nA; the variation range is 0.13nAp−p.Conclusion: A method of fast and accurate current measurement as low as 50pA using IV conversion and DC-AC conversion in ATE environment has been developed.
Keno Sato, Takayuki Nakatani, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Jiang-Lin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001
ATS7
2021 Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
abstract
This paper demonstrates the harmonic distortion measurement of operational amplifiers by applying our proposed summing node method; we show that it can provide low-cost and high-accuracy testing at the mass production shipping stage. Experiments show that measurement accuracy below -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations, and experiments that the summing node method makes the measurement accuracy robust to the harmonics of the signal source providing the sinusoidal input signal to the operational amplifier under test. In other words, a high precision signal generator is not required. Furthermore, we propose the false summing node method, which does not require direct probing of the summing node, in order to avoid oscillation and instability of the video-band operational amplifier under test. Simulations and experiments verify that it can achieve accurate testing without probing of the summing node and it is robust against the ratio variation of the two resistors in the false summing node testing circuit.
Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei, Minh Tri Tran 0001, Kazumi Hatayama, Haruo Kobayashi 0001
ITC4
2020 Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers
abstract
This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.
Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jiang-Lin Wei, Jianlong Wang, Kazumi Hatayama, Haruo Kobayashi 0001
ATS1