Physical design watermarking (WM) on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. This article presentsICMarks, a quality-preserving and robust WM framework for modern IC physical design.ICMarksembeds unique watermark signatures during the physical design’s placement stage, thereby authenticating the IC layout ownership.ICMarks’s novelty lies in 1) strategically identifying a region of cells to watermark with minimal impact on the layout performance and 2) a two-level WM framework for augmented robustness toward potential removal and forging attacks. Extensive evaluations on benchmarks of different design objectives and sizes validate thatICMarksincurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, we demonstrateICMarksis robust against two major WM attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the WM schemes, the signatures cannot be removed without significantly undermining the layout quality.

Placement plays a pivotal role in the modern FPGA physical design flow to determine the locations of the design instances among the available FPGA device resources, impacting routability and performance. Due to the lack of open-source accurate timing models for high-performance FPGAs, academic placement research has focused primarily on wirelength opti- mization rather than timing optimizations. This work presents an open-source timing-driven FPGA placer accelerated on GPU that employs a congestion-aware and data-driven timing model with timing optimizations at global placement and legalization. The placement objective incorporates an additional term to optimize the timing arcs in the lagrangian formulation. While packing and legalizing look-up tables (LUTs) and flip-flops (FFs), we emphasize timing-critical nets to remain within the Slice, minimizing overall path delay. On the ISPD'2016 contest benchmarks employing an AMD-Xilinx UltraScale architecture, our placer is 3× faster than the commercial AMD Vivado with similar critical path delay (×1.02) and 40% faster routing runtime.

Placement is a critical step in the FPGA design implementation flow that strongly impacts routability and timing closure. Recent state-of-the-art academic analytical placers have achieved impressive scalability but are limited to AMD Ultrascale-like architectures and mostly synthetic designs. On the other hand, VPR, the place and route tool within the widely used open-source Verilog-to-Routing (VTR) toolchain, can produce a legal placement for any arbitrary architecture; however, its simulated annealing placer scales poorly. Thus, there is a clear need to bring scalable, high-quality placement to realistic architectures and circuits. In this work, we develop a hybrid framework that combines the strength of a scalable flat analytical placer with the flexibility of simulated annealing techniques to adapt to various architectures and circuits, substantially improving the quality of results. We augment the state-of-theart analytical elfPlace FPGA placer as aug-elfPlace, generalizing its architecture modeling to handle real-world constraints and target different and more complete architectures. We leverage VPR’s legalization capability to integrate with external placers such as aug-elfPlace. VPR’s simulated annealing placer can further optimize the legalized placement, and VPR’s router and timing analysis can provide final quality results. By integrating wirelength-driven aug-elfPlace and VPR, our hybrid framework achieves up to 2% timing improvement with 15% reduction in routed wirelength compared to timing-driven VPR, on average across the large and heterogeneous Titan23 benchmark suite targeting an Intel Stratix-IV-like architecture.

Placement plays a pivotal and strategic role in the FPGA implementation flow to allocate the physical locations of the heterogeneous instances in the design. Among the placement stages, the packing or clustering stage groups logic instances like look-up tables (LUTs) and flip-flops (FFs) that could be placed on the same site. The legalization stage determines all instances' physical site locations. With advances in FPGA architecture and technology nodes, designs contain millions of logic instances, and placement algorithms must scale accordingly. While other placement stages - global placement and detailed placement, have been accelerated using GPUs, the acceleration of packing and legalization stages on a GPU remains largely unexplored. This work presents DREAMPlaceFPGA-PL, an open-source packer-legalizer for heterogeneous FPGAs that employs GPU for acceleration. We revise the existing consensus-based parallel algorithms employed for packing and legalizing a flat placement to obtain further speedup on a GPU. Our experiments on the ISPD'2016 benchmarks demonstrate more than 2× acceleration.

Modern Field Programmable Gate Arrays (FPGAs) are large-scale heterogeneous programmable devices that enable high performance and energy efficiency. Placement is a crucial and computationally intensive step in the FPGA design flow that determines the physical locations of various heterogeneous instances in the design. Several works have employed GPUs and FPGAs to accelerate FPGA placement and have obtained significant runtime improvement. However, with these approaches, it is a non-trivial effort to develop optimized and algorithmic-specific kernels for GPU and FPGA to realize the best acceleration performance. In this work, we present DREAMPlaceFPGA, an open-source deep-learning toolkit-based accelerated placement framework for large-scale heterogeneous FPGAs. Notably, we develop new operators in our framework to handle heterogeneous resources and FPGA architecture-specific legality constraints. The proposed framework requires low development cost and provides an extensible framework to employ different placement optimizations. Our experimental results on the ISPD'2016 benchmarks show very promising results compared to prior approaches.