Event cameras have gained significant attention due to their bio-inspired properties, such as high temporal resolution and high dynamic range. However, obtaining large-scale labeled ground-truth data for event-based vision tasks remains challenging and costly, which hinders the development of the event-based algorithm. In this paper, we present ControlEvents, a diffusion-based generative model designed to synthesize unlimited high-quality event data guided by diverse control signals such as class text labels, 2D skeletons, and 3D body poses. Our key insight is to leverage the diffusion prior from foundation models, such as Stable Diffusion, enabling high-quality event data generation with minimal fine-tuning and limited labeled data. Our method streamlines the data generation process and significantly reduces the cost of producing labeled event datasets. We demonstrate the effectiveness of our approach by synthesizing event data for visual recognition, 2D skeleton estimation, and 3D body pose estimation. Our experiments show that the synthesized labeled event data enhances model performance in all tasks. Additionally, our approach can generate events based on unseen text labels during training, illustrating the powerful text-based generation capabilities inherited from foundation models.

Leveraging diffusion models, 3D LiDAR scene generation has achieved great success in both range-view and voxel-based representations. While recent voxel-based approaches can generate both geometric structures and semantic labels, existing range-view methods are limited to producing unlabeled LiDAR scenes. Relying on pretrained segmentation models to predict the semantic maps often results in suboptimal cross-modal consistency. To address this limitation while preserving the advantages of range-view representations, such as computational efficiency and simplified network design, we propose Spiral, a novel range-view LiDAR diffusion model that simultaneously generates depth, reflectance images, and semantic maps. Furthermore, we introduce novel semantic-aware metrics to evaluate the quality of the generated labeled range-view data. Experiments on SemanticKITTI and nuScenes datasets demonstrate that Spiral achieves state-of-the-art performance with the smallest parameter size, outperforming two-step methods that combine the best available generative and segmentation models. Additionally, we validate that Spiral’s generated range images can be effectively used for synthetic data augmentation in the downstream segmentation training, significantly reducing the labeling effort on LiDAR data.

Stochastic computing (SC) has emerged as a promising computing paradigm for neural acceleration. However, how to accelerate the state-of-the-art Vision Transformer (ViT) with SC remains unclear. Unlike convolutional neural networks, ViTs introduce notable compatibility and efficiency challenges because of their nonlinear functions, e.g., softmax and Gaussian Error Linear Units (GELU). In this paper, for the first time, a ViT accelerator based on end-to-end SC, dubbed ASCEND, is proposed. ASCEND co-designs the SC circuits and ViT networks to enable accurate yet efficient acceleration. To overcome the compatibility challenges, ASCEND proposes a novel deterministic SC block for GELU and leverages an SC-friendly iterative approximate algorithm to design an accurate and efficient softmax circuit. To improve inference efficiency, ASCEND develops a two-stage training pipeline to produce accurate low-precision ViTs. With extensive experiments, we show the proposed GELU and softmax blocks achieve 56.3% and 22.6% error reduction compared to existing SC designs, respectively, and reduce the area-delay product (ADP) by 5.29 x and 12.6 x, respectively. Moreover, compared to the baseline low-precision ViTs, ASCEND also achieves significant accuracy improvements on CIFARI0 and CIFARI00.

End-to-end stochastic computing (SC) emerges as a promising paradigm for efficient neural acceleration. However, existing serial SC accelerators face serious accuracy challenges due to errors in addition, limited activation compatibility, and limited bitstream multiplication. In this paper, we propose OSCA, an accurate yet efficient end-to-end serial SC accelerator. OSCA features fine-grained scaling control in the SC adder to minimize quantization error and introduces novel segment units for piecewise approximation of complex nonlinear activation functions. We also design an integer-bitstream multiplier that guarantees accuracy regardless of the correlation between input bitstreams. Compared to the serial baseline accelerator of INT8 precision, we can achieve a 30.18% reduction in root mean square error (RMSE) along with an 87.75% area-delay product (ADP) reduction. Moreover, compared to a more accurate parallel accelerator, OSCA achieves a 92.05% ADP reduction with a 12.54× improvement in area efficiency, while also increasing inference accuracy by 0.44% and 0.86%.

End-to-end stochastic computing (SC) enables fault-tolerant and area-efficient neural acceleration by conducting non-linear addition, including accumulation and activation functions, in SC bitstreams. However, existing non-linear adder designs suffer from a high hardware cost, accounting for a major portion of the datapath power and area, and may also have limited computation accuracy and flexibility. In this paper, we propose an accurate yet efficient non-linear adder design. We analyze the redundancy in existing designs and propose a parameterized approximate non-linear adder design space. By systematic design space exploration, we develop non-linear adders that are significantly more efficient than existing designs with negligible computation error. We further propose a spatial-temporal architecture to improve the design flexibility and efficiency for a wide range of network sizes. To support state-of-the-art networks, e.g., ResNet18, we demonstrate that our design can reduce the datapath area by 2.16× compared with the baseline designs. Our design can also reduce the area-delay product (ADP) of the non-linear adder by 4.13× and 23.29× for large and small convolution layers in ResNet18, respectively.

Stochastic computing (SC) emerges as a fault-tolerant and area-efficient computing paradigm for neural acceleration. However, existing SC accelerators suffer from an intrinsic trade-off between inference accuracy and efficiency: accurate SC re-quires high precision computation but suffers from an exponential increase of bitstream length and inference latency. In this paper, we discover the high precision residual as a key remedy and propose to combine a low precision datapath with a high precision residual to improve inference accuracy with minimum efficiency overhead. We also propose to fuse batch normalization with the activation function to further improve the inference efficiency. The effectiveness of our proposed method is verified on a recently proposed SC accelerator. With extensive results, we show that our proposed SC-friendly network achieves 9.43% accuracy im-provements compared to the baseline low precision networks with only 1.3% area-delay product (ADP) increase. We further show$\boldsymbol{3.01\times}$ADP reduction compared to the baseline SC accelerator with almost iso-accuracy.

A popular way to implement an arithmetic function is through a lookup table (LUT), which stores the pre-computed outputs for all the inputs. However, its size grows exponentially with the number of input bits. In this work, targeting at computing kernels of error-tolerant applications, we propose DALTA, a reconfigurable decomposition-based approximate lookup table architecture, to approximately implement those kernels with dramatically reduced size. We also propose integer linear programming-based approximate decomposition methods to map a given function to the architecture. Our architecture features with low energy consumption and high speed. The experimental results show that our architecture achieves energy and latency savings by 56.5% and 92.4%, respectively, over the state-of-the-art approximate LUT architecture.

In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%-98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.

Recently, due to the high fault tolerance and low hardware cost, stochastic computing (SC)-based neural network (NN) accelerators have been widely studied. One big challenge of it is the implementation of accumulation and activation function. The existing designs have problems of low accuracy and high energy consumption. In this paper, based on a special type of stochastic encoding, the parallel thermometer coding, we propose an accurate design for the combination of the accumulation and non-linear function, which is called a non-linear adder. Dedicated designs for the non-linear adders with the common activation functions such as hyperbolic tangent (tanh), logistic (or sigmoid), and rectified linear unit (ReLU) are proposed using the bitonic sorting network and the selective interconnect. The experimental results show that, at the cost of the area, the proposed nonlinear adder achieves more than three orders of magnitude improvement in accuracy and at least 44.5× energy consumption reduction compared with the traditional designs.