Time-based analog-to-digital converters (ADCs) have recently gained attention because of their ability to reach high sample rates with good energy efficiency. The performance of most implementations is limited by the Voltage-to-Time Converter (VTC), hence necessitating thorough analysis on its performance. This paper derives expressions for the noise and linearity of a constant-slope VTC. The derived expressions provide an explicit link between the circuit parameters and VTC performance as well as offer insight on the available trade-offs. Based on the expressions, a general design methodology for constant-slope VTCs is proposed. The simulated verification with 28-nm CMOS shows good agreement with the presented analysis and with previously measured results, thereby corroborating the proposed design methodology. The presented design methodology allows the developed understanding between the VTC circuit parameters and performance metrics to be utilized in e.g. design exploration and algorithmic circuit optimization to find an optimal set of parameters for a given target specification.

Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.

Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cyclic-coupled ring oscillators (CCROs) as a time-domain quantizer to achieve a combination of subgate-delay time resolution together with a short conversion time, thereby enabling data conversion with high resolution as well as high bandwidth. The resolution-power tradeoff in coupled oscillators is studied. Simulation indicates up to a factor-of-13 subgate-delay time resolution with 13 coupled oscillators. A real-time quantizing time-to-digital converter with coupled oscillators is designed for a time-domain analog-to-digital converter. Powered by a factor-of-8 subgate-delay time resolution of 1.6 ps obtained with nine coupled oscillators, and a sample time of 4 ns for 11-bit conversion, the converter delivers a 9.9-bit ENOB over a signal bandwidth of 125 MHz and an SFDR of 88 dB. Results demonstrate that CCROs is an attractive candidate as a high-precision high-linearity time-domain quantizer for data converters.

A digital-friendly approach to implement injection-locked ring oscillators is proposed. We show that lock can be achieved by dynamically switching the delay of a delay element in a ring oscillator. A logic gate that generates the control signal for switching the delay, together with a one-bit controlled oscillator, inherently realizes a locking mechanism. Measurement results from a prototype circuit fabricated with a 28 nm CMOS process demonstrate the feasibility of the concept. The circuit with a measured lock range of 2.4-3.7 GHz occupies an area of 0.00043 mm2and consumes 0.18 mW power.