This design contest document proposes a low quiescent current low-dropout regulator (LDO) with an auxiliary amplifier, flipped voltage follower (FVF)-based power supply rejection ratio enhanced circuit (FBPEC) for electroencephalogram (EEG) recording devices. A FVF filter, current mirror, and common-source amplifier are employed to configure the FBPEC. The FBPEC employs the characteristics of the FVF filter to reduce the current consumption and increase the gain at specific frequencies. A 0.18 μm CMOS process is used to design and fabricate the proposed LDO. Compared to the general configuration LDO by measurement results, the proposed LDO exhibits an enhanced power supply rejection ratio (PSRR) up to 18 dB at frequencies exceeding 8 kHz. Moreover, the quiescent current of the proposed LDO at no-load is 648 nA. The proposed LDO exhibits a good figure-of-merit score compared to those of previous works, suggesting that the proposed circuit is an effective solution for use in wearable low-power EEG recording devices.

In this design contest document, measurement results demonstrate the effectiveness of a designed low current consumption amplifier for a compressed-sensing (CS) framework in wearable electroencephalography (EEG) recording devices. When reconstructing with a frequency bases, the reduction of biased 1/f noise is more important than frequency-unbiased white noise. Therefore, we designed an amplifier that reduces 1/f noise rather than white noise, while reducing power consumption, and employed it in the system. The designed amplifier is based a capacitively coupled chopper instrumentation amplifier (CCIA) architecture which used for low-noise amplifier (LNA). According to measurements of the designed CCIA, the power consumption is 0.36 μW/channel, it has the lower power consumption compared to amplifiers designed for similar applications in the past. The input referred noise (IRN) excluding the hum of the power supply was 3.3 μVrms. The measured IRN and simulations were used to confirm the effect of noise from CCIA on the CS-based EEG measurement framework. The difference in the normalized mean squared error at CR = 4 to the uncompressed conditions is 0.008. This result shows that even with the LNA specialized for low power consumption, a slight signal degradation is observed when the compression ratio is increased up to 4 in the CS framework by making use of the sparsity of EEG in the frequency domain.

This study presents a solution to achieve low power consumption by the intermittent operation of low-noise amplifiers (LNAs) for wireless electroencephalographs, that need a smaller battery. The LNA operates intermittently synchronized with the sampling timing of the analog-to-digital converter (ADC) by using the random undersampling matrix utilized in a previously proposed compressed sensing (CS) electroencephalogram measurement system. Designed using a 0.18 μm CMOS process, the LNA includes an intermittent operation circuit. The simulation results, the start-up time of the LNA was set to 4ms and the intermittent operation was performed at compression ratio of 4.17 based on a sampling frequency of 200Hz. The intermittent operation reduced power consumption by 58% compared to constant operation. The normalized mean square error (NMSE) was used to evaluate the influence of intermittent LNA operation on the reconstruction accuracy of CS. The difference in NMSE between intermittent and constant operation was only 9% on average over 25 frames. This indicates that intermittent operation minimally influenced the reconstruction accuracy.