The development of non-volatile Compute-In-Memory (nvCIM) technology has demonstrated significant potential in addressing the data movement and Multiply-and-Accumulate (MAC) bottlenecks in machine learning algorithms by enabling parallel analog Vector-Matrix Multiplication (VMM) operations directly within memory arrays. In this work, we introduce SPIKA, a fully integrated RRAM-CMOS chip designed for neural network acceleration. The key innovation of SPIKA lies in its ability to efficiently transfer input signals to output signals with minimal circuit overhead. The VMM operation is performed in the time domain, with the dot product accumulated on a switched capacitor, eliminating the need for high-resolution, power-intensive data converters. Implemented using commercially available 180nm technology, SPIKA operates on a 64×128 crossbar and utilizes 4-bit inputs, ternary weights, and 5-bit outputs. The chip is evaluated on the MNIST dataset, achieving a peak throughput of 1092 GOPS and an energy efficiency of 195 TOPS/W.

In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.

In general, intelligent systems require knowledge databases storing memory associations for mimicking the capabilities of the human brain. Conventional associative memory cells are constructed based on SRAM, a type of volatile memory consisting of large numbers of transistors per stored bit. Here, we present an energy efficient, robust and hardware friendly- associative memory cell design that we designate RC-XNOR-Z. It is based on creating a tuneable RC constant with the help of a modifiable resistance element (RRAM), plus a simplified XNOR gate for generating the output. The overall design has a total component count of 6T1C1R (6 transistors, 1 capacitor, 1 RRAM device), is non-volatile, is designed to work with RRAM devices with very low ON/OFF ratio (≈4), avoids high current DC paths during misses and operates under power supply of 0.95V. Furthermore, we show expected simulated power dissipation per miss including refresh in the order of single-digit nW/bit and power dissipation/hit in the order of 10 μW, which for a clock rate of 1GHz translates into aJ and 100s of pJ dissipation accordingly. This is competitive with state of art DRAM and SRAM.

Memristor crossbar arrays offer a novel new approach for designing high density non-volatile memory; however, precise measurement of resistive crossbar elements requires parallel current sensing capability not found in existing instruments. To provide this capability, we have designed and built an FPGA-based crossbar control instrument with independent per-channel biasing and measuring. In this paper, we cover the architecture of this new instrument, its operation and interface, and the results of testing conducted on the instruments pulse driver circuitry.

In this demonstration, we present a new electro-forming process, along with a new instrument to support this procedure. Memristor arrays will be available for the user to electroform, write, and read the resulting resistive state of the devices.