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Stefano Zanardi

dblp:283/0295 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 53% Hardware reliability and fault tolerance · 32% Integrated circuit design · 16%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › flash and SSD
flash memory		 0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
Integrated circuit design
digital circuit design		 0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
Hardware reliability and fault tolerance › error correction
error-correcting codes		 0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
Hardware reliability and fault tolerance › redundancy
redundancy management		 0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
YearPublicationVenuePosition
2003 An overview of logic architectures inside flash memory devices
abstract
In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.
Andrea Silvagni, Guiseppe Fusillo, Roberto Ravasio, Massimiliano Picca, Stefano Zanardi
 Proc. IEEE5