This paper presents a sub$-V_{\text{TH}}$ring oscillator (RO) based digital temperature sensor where the ROs are designed using the sub$-V_{\text{TH}}$transmission gates (TG). Two ROs are designed with different TGs to generate$f_{\mathrm{H}}$and$f_{\mathrm{L}}$frequencies, whose frequency ratio$(f_{\mathrm{H}}/f_{\mathrm{L}})$increases linearly with temperature. The temperature-dependent$f_{\mathrm{H}}/f_{\mathrm{L}}$ratio is converted to digital code (TCODE) using two asynchronous counters. Further, a cascoded 3T regulator is proposed to power the sensor and reduce its line sensitivity. The sensor prototype is designed in 180 nm while operated at 0.7 V supply it consumes 7.7 nW of power (3.6 nW by core and 4.1 nW by digital block) with$-1.5^{\circ}\mathrm{C}/+1.94^{\circ}\mathrm{C}$inaccuracy across 0°C to 100°C range after 2-point calibration at 10°C and 80°C. It achieves an 0.15°C resolution and FoM of 19 pJ-K2with 1.28 ° C/V line sensitivity when operated from 0.7 V to 2.2 V supply voltage.

This paper presents a current reference using temperature-compensated CMOS resistors. In the proposed circuit, the constant current is generated by compensating complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) CMOS resistors. The CMOS CTAT resistor is designed using a MOS biased in the deep-triode region. In contrast, the PTAT resistor is derived using the MOS biased in the sub-threshold triode region with a$\boldsymbol{V}_{\mathbf{TH}}-\mathbf{tracking}$voltage. The reference current is generated using a 3T regulator and the temperature-compensated CMOS resistors. The sensor prototype is designed in 180 nm for 172 pA of reference current$(\boldsymbol{I}_{\mathbf{REF}})$at a temperature coefficient (TC) of 327 ppm/ ° C from 0 ° C to 80 ° C. It has 0.63 nW power consumption at 1.1 V supply with an average line sensitivity of 0.63 %/V when operated from 1.1 V to 2.1 V supply voltage.

A 0.13 nW ultra-low-power over-temperature-protection circuit is proposed for highly integrated System-on-Chips (SoC). The circuit detects a temperature of $120^{\circ} \text{C}$ but can be programmed for other temperature thresholds. The temperature detection is achieved by comparing a reference voltage with a 2-transistor ultra-low-power inverter architecture. The 2transistor inverter is designed to have a proportional-to-absolute-temperature (PTAT) threshold characteristic, and the reference voltage is generated on-chip with a 2-transistor reference. The design is implemented in $0.18 \mu \text{m}$ CMOS technology and occupies an area of $0.0117 \text{mm}^{2}$. The design operates from 0.5 V supply voltage and has a line sensitivity of $0.1^{\circ} \text{C}/\text{V}$ and a hysteresis width of $7.7^{\circ} \text{C}$, as seen from simulations. The trim-free design has a worst-case process variation of 4%.

A picowatt programmable CMOS-based voltage reference (VR) for wireless sensor nodes (WSNs) is proposed in this work. It uses a pMOS current source and an nMOS current sink to generate a temperature-independent output voltage. A body bias potential is used to control the threshold voltage of the nMOS current sink to generate programmable output voltage. The architecture can achieve temperature compensated reference voltages for different temperature characteristics of body bias with the help of digital trimming. The body bias is generated on-chip using a dedicated body bias generation block. The prototype circuit is fabricated in the 0.18-$\mu \text{m}$CMOS process with deep-n-well (DNW) and occupies a total area of 0.022 mm2including the body bias block and a 10-pF decoupling MIM capacitor. The circuit provides output voltages from 250 to 370 mV. A total of ten chips from two different wafers (five chips per wafer) were measured. The average temperature coefficient (TC) is measured to be 72.17 ppm/$^\circ \text{C}$over$- 40\,\,^\circ \text{C}$to 80$^\circ \text{C}$for a reference voltage of 349.7 mV. The average line sensitivity (LS) obtained is 0.093%/V with a power supply rejection (PSR) of −39 dB at 100 Hz.

A 192 pA current reference is proposed for ultra-low-power applications. The sub-threshold design based circuit employs three-transistor-regulators to provide a CTAT (complimentary-to-absolute-temperature) source to gate voltage, to a PMOS device that minimizes the temperature variation of the reference current. Consistent performance across process variations is achieved through digital trimming and body bias control. A temperature coefficient (TC) of 542 ppm/ °C is attained at nominal process with a minimum and maximum TC of 350 ppm/ °C and 729 ppm/ °C, respectively, across all process corners. The circuit operates at a worst case minimum supply voltage of 700 mV and the power consumption is 1.06 nW at the nominal process and temperature. The same architecture is reused for a reference current of 87.7 nA, which improves the TC to 91.2 ppm/ °C. The circuit is designed in standard 0.18 μm CMOS technology.