The ordered statistics decoding (OSD) algorithm has been gaining popularity for ultra-reliable and low-latency communication (URLLC) scenarios due to its near-maximum likelihood decoding performance, especially for short linear block codes. However, its substantial computational complexity hinders practical applications. In this paper, we introduce an advanced hybrid OSD algorithm that fully utilizes the hard-decision algebraic decoding results to selectively activate soft-decision OSD operations, significantly mitigating computational complexity. Through a rigorous analysis of error-correction characteristics, we derive a theoretical condition under which the hybrid OSD algorithm guarantees superior error-correction performance over the baseline OSD. To apply the proposed hybrid algorithm to the emerging URLLC systems, we also present a novel decoder architecture that efficiently integrates hard-and soft-decision operations. For (127, 64) BCH codes, the prototype decoder in a 28-nm process achieves an average processing latency of 773 ns at a target block error rate of 10-5, improving information throughput by 4.2× and energy-efficiency by 35× and offering coding gain compared to previous OSD hardware designs.

Gait abnormalities are common in the older population owing to aging- and disease-related changes in physical and neurological functions. Differentiating the causes of gait abnormalities is challenging because various abnormal gaits share a similar pattern in older patients. Herein, we propose a deep neural network (DNN) model to classify disease-specific gait patterns in older adults using commercialized instrumented insoles. This study included 150 patients aged ≥ 65 years, divided into the following five groups (N = 30 in each group): healthy older individuals (HI), patients with Parkinson's disease (PD), patients with spastic hemiplegic gait due to stroke (SH), patients with normal-pressure hydrocephalus (NPH), and patients with knee osteoarthritis (OA). Participants performed the timed up and go test (TUGT) wearing the commercialized instrumented insole, GDCA-MD (Gilon, Republic of Korea). Seven data streams were collected from each insole using a 3-axis accelerometer and four pressure sensors and were analyzed. First, the statistical differences among groups in spatiotemporal features during TUGT, such as step count, step length, velocity, acceleration, regularity, and symmetricity, were examined. Second, a two-stage DNN model was developed that distinguishes HI from others in the first network and classifies the pathologic groups in the second network. The areas under the curve were 0.96, 0.88, 0.98, 0.96, and 0.97 for identifying HI, PD, OA, SH, and NPH, respectively. We demonstrated that the proposed DNN model can reliably classify gait abnormalities in an older population using simple instrumented insoles and a test.

The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization.

Due to an iterative nature, a low-density parity-check (LDPC) decoder is associated with a long latency, being a major bottleneck of the baseband processor in wireless communication systems. Based on the practical min-sum (MS) decoding method, in this paper, we present a cost-effective algorithm for reducing the processing latency of LDPC decoders. By checking the number of short-length cycles in the LDPC code structure, the proposed method dynamically changes the reweighting factor at the iterative operations, successfully reducing the average number of iterations. In addition, we present several optimization schemes to mitigate the hardware overheads resulting from the proposed reweighting scheme. In a 65-nm CMOS process, a prototype IEEE 802.11ay LDPC decoder optimized by the proposed schemes reduces the decoding latency by 1.7 times with negligible overheads compared with the contemporary designs.