Recent advances in CMOS technology have enabled the implementation of high-performance and energy-efficient digital-intensive radio transceivers for fifth-generation (5G) and beyond (6G) wireless communication systems. Among the various transmitter architectures, the outphasing transmitter with constant-amplitude modulation, which allows the use of highly energy-efficient nonlinear power amplifiers, has garnered significant attention since it easily lends itself to a digital-intensive implementation, thus fully exploiting the benefits of scaled CMOS technologies. However, an outphasing transmitter with a delay-based phase modulator suffers from performance degradation due to mismatch-induced static nonlinearity. This paper presents a linearization algorithm that minimizes mismatch-induced static nonlinearity by reordering the unary-weighted delay elements. The effectiveness of this algorithm is demonstrated through simulations and its application to measured delay characteristics from a 22-nm FDSOI CMOS transmitter prototype in a system simulation. The proposed reordering algorithm results in a 7.94% points improvement from 10.63% in EVM and a 7.76dB enhancement from 25dB in ACLR for a 5G NR 64-QAM OFDM waveform with a 200MHz bandwidth.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency divider circuit, accompanied with an accumulator that controls the division count. The circuit is capable of operating as an integer or as a fractional divider. Key topic of this paper is the merging of div-2/3 and div-3/4 circuits into a single compact circuit that solves an issue of a forbidden state in fractional-division operation. The circuit is designed with 28-nm CMOS technology and the post-layout simulations indicate an operating input frequency range of 0.3 - 5.4 GHz with 13-bit fractional frequency resolution between division ratios of 2-4. The divider occupies only 40 pm × 30 pm while consuming 2.0 mW at 5.4 GHz input frequency.

This paper describes the design and measurement of an open-loop fractional frequency divider implementation. The fractional divider consists of a multi-modulus integer frequency divider (MMD), a sigma-delta modulator (SDM) and a pipelined phase interpolator. The fractional frequency division is achieved with the MMD and the 13-bit SDM toggling the integer division ratio. The resulting signal is then processed by the phase interpolator which significantly reduces the spurs by 22 dB and generates spectrally clean signal with correct output frequency. The prototype is implemented in 28-nm CMOS technology and it operates within input frequency range of 1.9 GHz - 3.5 GHz with fractional division ratio in between 2-3. As an example of the operation, with a setting of an arbitrary division ratio of 2.3164 and input frequency of 2.4 GHz, the output sets correctly to 1.0361 GHz with RMS jitter of 2.1 ps.