Demo Data from EDBT 2026 / reviewers in the wild / expert
Shiva Thiagarajan
dblp:283/6596 · also Shiva Shankar Thiagarajan
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2022
0000-0002-0427-3773ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 61% Electronic design automation · 39% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
defect tolerance |
0.6 | 1 | 2022 | A defect tolerance framework for improving yield · DAC 2022 |
Electronic design automation
logic synthesis |
0.6 | 1 | 2022 | A defect tolerance framework for improving yield · DAC 2022 |
Hardware reliability and fault tolerance
timing error tolerance |
0.6 | 1 | 2022 | A defect tolerance framework for improving yield · DAC 2022 |
Electronic design automation › design for manufacturability › design for yield
yield enhancement |
0.2 | 1 | 2022 | A defect tolerance framework for improving yield · DAC 2022 |
Methods — techniques the papers use, named apart from their topics
static timing analysis · 0.6defect-aware library generation · 0.6cell characterization · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | A defect tolerance framework for improving yieldabstractIn the latest technology nodes, there is a growing concern about yield loss due to timing failures and delay degradation resulting from manufacturing complexities. Largely, these process imperfections are fixed using empirical methods such as layout guidelines and process fixes which come late during the design cycle. In this work, we propose a framework for improving the design yield by synthesizing netlists with improved ability to withstand delay variations to reduce yield loss. We advocate a defect tolerant approach during early design stages to synthesize netlists by introducing defect-awareness to EDA synthesis, thereby generating robust netlists that can withstand delays induced by process imperfections. Toward this objective, we present a) a methodology to characterize standard library cells for delay defects to model the robustness of the cell delays, and b) a solution to drive design synthesis using the intelligence from the cell characterization to achieve design robustness to timing errors. We also introduce defect tolerance metrics to quantify the robustness of standard cells to timing variations, which we use to generate defect-aware libraries to guide defect-aware synthesis. Effectiveness of the proposed defect-aware methodology is evaluated on a set of benchmarks implemented in GF 12nm technology using static timing analysis (STA), revealing a 70--80% reduction of yield loss due to timing errors arising from manufacturing defects, with minimum impact on the area, power and no impact on performance. Shiva Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris |
DAC | 1 |
| 2022 | Efficient CNN-Based Super Resolution Algorithms for Mmwave Mobile Radar ImagingabstractIn this paper, we introduce an innovative super resolution approach to emerging modes of near-field synthetic aperture radar (SAR) imaging. Recent research extends convolutional neural network (CNN) architectures from the optical to the electromagnetic domain to achieve super resolution on images generated from radar signaling. Specifically, near-field synthetic aperture radar (SAR) imaging, a method for generating high-resolution images by scanning a radar across space to create a synthetic aperture, is of interest due to its high-fidelity spatial sensing capability, low cost devices, and large application space. Since SAR imaging requires large aperture sizes to achieve high resolution, super-resolution algorithms are valuable for many applications. Freehand smart-phone SAR, an emerging sensing modality, requires irregular SAR apertures in the near-field and computation on mobile devices. Achieving efficient high-resolution SAR images from irregularly sampled data collected by freehand motion of a smartphone is a challenging task. In this paper, we propose a novel CNN architecture to achieve SAR image super-resolution for mobile applications by employing state-of-the-art SAR processing and deep learning techniques. The proposed algorithm is verified via simulation and an empirical study. Our algorithm demonstrates high-efficiency and high-resolution radar imaging for near-field scenarios with irregular scanning geometries. Christos Vasileiou, Josiah W. Smith, Shiva Thiagarajan, Matthew Nigh, Yiorgos Makris, Murat Torlak |
ICIP | 3 |