Today’s logic chips and System-on-Chips (SoCs) are ever-growing in size, complexity, and integration density. This drives a continuous need to develop novel and advanced ways to efficiently test such devices after manufacturing. High-bandwidth IJTAG over SSN (HB-IJTAG) is one such innovation that leverages the high-speed and parallel Streaming Scan Network (SSN) bus to concurrently access many local IEEE 1687 (IJTAG) networks.However, every time the high-bandwidth IJTAG access mode is activated, it must first be configured through the global IJTAG network. The initial configuration and subsequent reconfigurations constitute a substantial test time overhead due to the lower shift speed and serial nature of global IJTAG.This paper introduces wide-ranging enhancements to the high-bandwidth IJTAG access to allow for persistent utilization of the high-speed SSN bus. By eliminating the reasons for the expensive reconfigurations, high-bandwidth IJTAG can remain active throughout the entire test session. This results in a significant reduction of test setup time and more efficient test delivery. Our experiments clearly demonstrate these benefits in different pattern delivery scenarios. Persistently using the high-bandwidth data delivery reduced the relevant IJTAG pattern execution time by up to 243x, yielding an up to 18x lower overall test time for SSN ATPG patterns.

The increasing complexity of Integrated Circuits (ICs) is driven by heterogeneous functionality and stringent performance demands. This necessitates scalable and efficient design for testability (DFT) solutions to ensure cost-effective test access and functional correctness. Streaming Scan Network (SSN) and High-Bandwidth IJTAG over SSN (HB-IJTAG) enhance the test efficiency significantly by accelerating the data transfer and optimizing the test execution. However, these technologies introduce validation challenges due to more intricate control mechanisms and their large-scale deployment.This paper presents a novel, holistic approach for generating and sequencing functional validation patterns. These patterns systematically leverage SSN and HB-IJTAG capabilities to optimize overall efficiency. The proposed methodology enables the concurrent and robust validation of hundreds of SSN and HB-IJTAG DFT components, significantly improving the overall test execution time.

As Systems-on-Chip (SOC) designs grow in complexity, so do the challenges associated with testing them. Some of the obstacles SOC designers face include limited I/O and scan channels, routing and timing closure issues, increasing manufacturing test and defect diagnosis time, and growing test data volume. Various design-for-test (DFT) techniques exist to handle complex SOC designs that have multiple cores. One new DFT implementation technique is the streaming scan network (SSN) high-bandwidth parallel data bus. SSN addresses many of the SOC challenges by providing an optimized packet-based scan data delivery system. It also dynamically optimizes test time by adjusting the data applied to each core. However, SSN is limited to delivering scan data; it cannot be used to deliver data to individual instruments in a physical block using the IEEE 1687 (IJTAG) network. This paper introduces a new high-bandwidth IJTAG DFT technology that leverages the existing high-speed parallel SSN bus to drive the serial IJTAG network. It describes the DFT implementation methodology, the impact to the backend in terms of timing and SDC, and how verification was done by Intel as they deployed it on multiple dielets in their next generation client CPU. Moreover, data on area overhead and the overall test cost savings achieved is presented.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

IEEE 1687 (IJTAG) provides significant value to the DFT engineer and efficiency in the DFT flow. However, IJTAG requires 4 or 5 pins to drive an IEEE 1149.1 compliant TAP controller. Many of our designs have fewer than 4 pins total, prohibiting the usage of IJTAG. In this paper we describe a solution that drives an embedded TAP controller from a chip interface that consists of only 2 ports, a clock port and a bidirectional data port. The embedded TAP then drives the IJTAG network as usual, providing us all the benefits of IJTAG. To enable this, we needed to expand the used EDA tool's IJTAG support in the direction of IEEE P1687.1. Experiences from the implementation of this solution in a productive chip show significant productivity gains.