High coverage ATPG scan structural testing is a defacto automotive industry test standard proven to very effectively screen logic gates suffering with hard defects. Cell- Aware (CA) testing goes further by injecting hard defects between transistor nodes inside standard cell gates and creating optimal test stimuli. However latent defects are notoriously difficult to expose even with CA tests, even when the tests run at extreme ‘Zero Defect’ test conditions (eg very low voltage or overclocked frequency). Such latent defects may escape into the field and fail in the application, and a major challenge is presented to chip suppliers to quickly diagnose and identify a test improvement on a mature volume production product. This paper describes a new approach to proactively, using simulation, achieve highly effective latent defect screening stimuli. By simulating the behavior of soft resistive defects on the circuit across voltage, process and temperature. The analysis shows that by taking the mathematical compliment of soft and hard defect stimuli found at nominal and Zero Defect simulation test conditions, the default cell aware stimuli can be incrementally optimized to efficiently screen latent defects and improve defective part per million/billion performance.

Executing scan tests at very-low voltage is a long-known industry best practice to screen resistive latent defects and contribute to enabling < 1 Defective Part Per Million (DPPM) performance for Automotive products. To be effective, it is necessary for these tests to run at near the intrinsic low voltage capability of the silicon. Slowing shift and capture clocks are best practices deployed to overcome Very-Low-Voltage (VLV) test timing limitations, but there are other challenges. This paper discusses two activities that enabled true VLV testing in a single digit FinFET technology. The first discusses a design implementation in the General-Purpose IO pads that supported correct signal level shifting at VLV and avoided action of low voltage detect circuitry during VLV testing. The second describes a series of design of experiments to characterize the test instrumentation at VLV conditions and optimize settings to robustly execute the tests at VLV conditions.

Cell-neighbor-bridging defects between logic and filler cells were detected on an automotive design after a highly resistive short defect was activated during an internal reliability assessment, having previously passed all wafer probe and package Final Test stresses and screens. The impacted cell’s nodes were confirmed to be stressed and tested as intended at the wafer probe insertion, but not sufficiently enough to activate and observe the effect of the highly resistive defect’s impact on the circuit behavior. The paper discusses a new methodology that identified and located all instantiations of the affected cell combinations in the sea of gates, and development of new stress and test stimuli using User Define Fault Models (UDFM) to target only the affected cell combinations. Limiting the reach of the enhanced stress and test in this way enabled a cost effective and high-quality solution to accelerate activation and improve detectability of the latent defect during silicon test flows.

High Voltage Stress Test (HVST) is critical for screening out latent defects to ensure quality on automotive semiconductor devices. This paper describes a novel way to adaptively adjust HVST stress voltage based on real-time current measurement to ensure every part is stressed reliably at the highest possible voltage within the tester hardware current limit as well as with equivalent extrinsic defect coverage on FinFET technologies.

Automotive ICs (Integrated Circuits) demand extremely high reliability and quality requirements. On the advanced technology nodes to enable autonomous driving with exploding amount of input/output (IO) data, more and more analog IO pads have been implemented on the automotive ICs, which pose a unique challenge on how to effectively and safely stress them to meet automotive Zero Defect (ZD) requirement. In this paper, we present a stress, test and simulation methodology on analog multi-voltage IOs in which the stress conditions are determined by circuit level reliability simulation while silicon stress results are used to correlate to the simulation models. Silicon results on 16nm FinFET automotive microprocessor are discussed to demonstrate the effectiveness of our methodology.