This paper presents a simple, low-cost temperature-to-digital-converter (TDC) with a wide operation range of $-55 ^{\circ}\text{C}$ to $200 ^{\circ}\text{C}$ and inaccuracy of $\pm 1.9 ^{\circ}\text{C}$. The proposed method relies on device and layout matching to cancel the effects of component temperature coefficients and I-V characteristic nonlinearities and to enable accurate temperature sensing. Additionally, the proposed method decreases the design complexity and significantly improves area requirements and conversion speed of the TDC. Moreover, in the proposed design, no complicated signal processing devices, such as analog-to-digital converters (ADCs), are used, further decreasing the cost in terms of area and energy per conversion. The design is implemented in 65nm CMOS technology with a supply voltage of 2.5V. The total area of this TDC is 0.007 mm $^{\mathbf{2}}$ with an ultra-low energy per conversion of 9nJ.

The number of electronic components in mission-critical applications is increasing rapidly and, with the dawn of electric vehicles, this increase is expected to accelerate in the near future. As functional safety (FuSa) is of utmost importance in these applications, the increasing demand for integrated circuits with zero defective parts per million (DPPM) is pressing the chip industry to achieve high defect coverage. In this paper, simple digital Design for Test (DfT) techniques are presented to detect defects in Low Drop-Out Regulators (LDO). The proposed method uses digital mismatch injection and digital-like detectors to detect various defects in an LDO. The digital nature of the proposed method can help reduce the test cost by avoiding expensive and time-consuming analog testing circuitry. Using spice simulations, we show that our method can detect up to 97.5% of the defects providing high defect-coverage. Additionally, as our injectors and detectors are simple in nature, they are not only area-efficient and easy-to-design but also easily scalable. Furthermore, in this work, we also introduce a simple and robust dual-threshold detector that can be used to monitor faults in biasing circuits.

This paper proposes a novel method for a structural test of the Successive Approximate Register (SAR) Analog to Digital Converter (ADC). The presented strategy has an ignorable area and power overhead and is implemented entirely digitally. We introduce simple digital checkers for the structural test of the sample and hold switch. Moreover, with no addition of extra circuitry and using the normal potential of the ADC we will perform a fast and localized fault detection for the heart of the ADC, capacitive DAC block. The BIST can be applicable as both post-production and in-field tests, capable of detecting zero-time defects and latent defects. The proposed BIST has zero to none area overhead, fast run time, 100% coverage, and is fully digital with no degradation of the normal operation and performance of the ADC.

An operational amplifier (op amp) is a fundamental block used extensively both as a stand-alone device and as a major block embedded in an SoC. To fully characterize an op amp, sophisticated analog and digital testing is required, which is expensive. Fault detection techniques have proved to reduce package cost and test cost by detecting faulty devices early in the test sequence. In this paper, a simple Design for Test (DfT) technique called intentional offset injection is proposed to detect various faults in the op amp. As our proposed method is completely digital, pure digital circuitry can be used, thereby avoiding expensive analog testing. The op amp can be tested with the proposed fault detection method during wafer probe test right after the continuity tests and the faulty devices could be discarded, thereby circumventing time-consuming analog testing. Additionally, our detection scheme can be used for power-on selftest after deployment and for online health monitoring during normal operation. We show that the proposed detection method can provide high fault coverage of 95% with modest area requirements. In this work, we also introduce a detector called digital window comparator which is used to monitor faults in the biasing circuit as well as in the Widlar current reference providing increased fault coverage.