ABSTRACT This article proposes a solution to the factorization problem in cryptographic systems by leveraging the steps of the Toom‐Cook algorithm for large‐number multiplication. This approach can factor a 200‐bit number, with performance varying depending on memory and processing power. Experiments demonstrate that the factorization problem in cryptography can be solved more efficiently by employing algorithms designed for fast and straightforward multiplication of large numbers. Examples include the Schönhage–Strassen algorithm, which is based on polynomials and Fourier transforms, the Fürer algorithm, the second Schönhage–Strassen algorithm using modular arithmetic, and Karatsuba's algorithm. This advancement significantly impacts modern computing and cryptography, enhancing both security and reliability. The proposed technique was extensively tested through simulations using the MATLAB simulator. Experimental results indicate improvements of 91% in efficiency and 95% in accuracy compared to state‐of‐the‐art techniques.

Abstract Quantum dot Cellular Automata (QCA) is a promising paradigm after CMOS technology due to low power consumption and small area requirements. As the counter is the most important and fundamental component of the QCA sequential logic family, therefore current effort has been made to design and analysis a dual‐mode counter. The reported dual‐mode nano counter can be operated as a Ring counter (R‐counter) as well as it can be operated as a Twisted‐ring counter (T‐counter). To achieve this, two inverters, four majority voters, and four D flip‐flops have been fully utilized. The main advantage of this design is that a single nano‐counter circuit can perform both tasks of R‐counter and T‐counter, which therefore eliminates the design constraint of double QCA layouts. In addition to that, the proposed 4‐bit QCA layout is easily expandable to n‐bit as per needs. With compared to the best‐reported design, the proposed dual‐mode counter has 75% and 29% less delay and cell count respectively. The area‐delay cost, QCA‐specific cost, and energy‐delay cost of the proposed circuit are approximately 13 times, 228 times, and 61 times superior to the previously reported best design. The designs were verified using the popular QCA layout design software QCADesigner 2.0.3. Simultaneously, two energy estimate tools, QCAPro and QCADesigner‐E (QDE), were utilized to investigate the circuits' energy dissipation.