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Jeonghwan Kang

dblp:284/3251 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2025
0000-0002-7567-0530ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Systems and software security · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security › memory safety
bounds checking
0.812024
Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M · DAC 2024
Systems and software security › memory safety
heap security
0.812024
Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M · DAC 2024
Systems and software security
memory safety
0.812024
Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M · DAC 2024
Embedded and real-time systems › embedded system security
firmware security
0.212024
Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M · DAC 2024

Methods — techniques the papers use, named apart from their topics

fat pointer · 1.5TT instructions · 1.5
YearPublicationVenuePosition
2025 ELK: Effective Lock-and-Key Technique for Temporal Memory Safety on Embedded Devices in ARMv8-M
abstract
Embedded devices built on microcontroller units (MCUs) power a vast array of safety- and performance-critical applications. Contrary to the long-held belief that resource-constrained embedded devices avoid dynamic allocations, recent studies show that heap use is actually common. Therefore, embedded software written in C/C++ is prone to temporal memory safety violations. The lock-and-key mechanism is a well-established defense for temporal memory safety. For high performance, recent studies embed keys directly in the unused high-order bits of 64-bit pointers, but this approach has been considered infeasible on MMU -less embedded devices. In this paper, we propose ELK, an effective lock-and-key technique for temporal memory safety on embedded devices in ARMv8-M. ELK observes that only the low-order bits of a 32-bit pointer are needed to access on-chip SRAM. Thus, ELK embeds keys in the unused middle-range bits of 32-bit pointers and stores locks inline with objects through size-aligned allocation that leverages ARMv8-M hardware features. Evaluating the ELK prototype shows geometric mean runtime overheads of 3.9% and 7.4 % on the BEEBs and MiBench2, respectively. The memory overhead, which represents the increase in peak heap usage, ranges from 0.1 % to 2.6 % across six heap-intensive applications. On the Juliet test suite, ELK detects all 180 temporal memory safety violations with zero false positives.
Jeonghwan Kang, Kyounghwan Kim, Donghyun Kwon
ACSAC1
2025 ROSec: Intra-Process Isolation for ROS Composition With Memory Protection Keys
abstract
Robot Operating System(ROS) is a software framework for robotic systems that includes various packages for developing robotic applications.Compositionis a package that combines multiple applications, namely,nodes, to be loaded and executed in a single process. However, permitting multiple nodes to share the address space could expand the attack surface such that vulnerabilities in a node are more likely to be exploited to subvert nodes running in the same space. We propose ROSec, an in-process isolation solution for ROS composition that utilizes Intel Memory Protection Keys. ROSecaims to enforce memory isolation between nodes within a process by preventing unauthorized access from one node to another. Unlike previous works that assume the number and sizes of nodes are statically defined and partitioned by developers, ROSecis designed to handle the dynamic nature of nodes that can be loaded and executed in a process at any time during execution. To achieve this, ROSecadopts a unique scheduling mechanism that utilizes theexecutor-centricexecution model of ROS to perform two main operations for MPK-based isolation:protection key assignmentandreassignment. Our evaluation shows that ROSeceffectively enforces in-process isolation while incurring a 6.4% performance overhead on a real-world application.Note to Practitioners—Cyber-Physical Systems are the core of modern applications, particularly robotics, as they integrate computing and physical processes. ROS necessitates real-time and security guarantees, which, unfortunately, trade-off with each other. While traditional ROS architecture relies on process isolation to separate various nodes, ROS2 introduces a feature called composition, which allows multiple nodes to run inside a single process, thus exposing various nodes to potential malicious compromises from others. This paper proposes a technique that utilizes Intel memory protection keys (MPK) to provide intraprocess isolation for ROS composition. Given that ROS nodes are dynamic, ROSEC provides key assignment and reassignment techniques to configure MPK dynamically.
Martin Kayondo, Jeonghwan Kang, Kyeongryong Lee, Donghyun Kwon, Yunheung Paek
IEEE Trans Autom. Sci. Eng.3
2024 Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M
abstract
Numerous embedded systems utilize firmware written in memory-unsafe C/C++. So, the firmware may exhibit spatial memory vulnerabilities, such as buffer overflows, which, if exploited by an attacker, can lead to various software attacks. While several studies have proposed defenses against these memory vulnerabilities, they often introduce significant performance and memory overhead or are impractical for application in embedded systems. In this paper, we introduce micro-fat pointer, a novel solution for heap memory safety for embedded systems. Notably, micro-fat pointer leverages TT instructions newly introduced in ARMv8-M to implement an efficient bounds-checking mechanism. Our evaluation results demonstrate that micro-fat pointer exhibits a 41% performance improvement compared to the existing state-of-the-art heap memory safety solution.
Jeonghwan Kang, Jaeyeol Park, Donghyun Kwon
DAC1