Demo Data from EDBT 2026 / reviewers in the wild / expert
Aditya Prasanna
dblp:284/3727
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0005-6595-2242ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 77% Parallel and multicore computing · 12% Memory systems · 11% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
synchronization |
0.3 | 1 | 2025 | RANGE-BLOCKS: A Synchronization Facility for Domain-Specific Architectures · ASPLOS (1) 2025 |
Memory systems › cache
cache organization |
0.2 | 1 | 2024 | METAL: Caching Multi-level Indexes in Domain-Specific Architectures · ASPLOS (2) 2024 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | RANGE-BLOCKS: A Synchronization Facility for Domain-Specific Architectures
Anagha M. Anil Kumar, Aditya Prasanna, Arrvindh Shriraman |
ASPLOS (1) | 2 |
| 2024 | METAL: Caching Multi-level Indexes in Domain-Specific ArchitecturesabstractState-of-the-art domain specific architectures (DSAs) work with sparse data, and need hardware support for index data-structures [31, 43, 57, 61]. Indexes are more space-efficient for sparse-data, and reduce DRAM bandwidth, if data reuse can be managed. However, indexes exhibit dynamic accesses, chase pointers, and need to walk-and-search. This inflates the working set and thrashes the cache. We observe that the cache organization itself is responsible for this behavior. Anagha M. Anil Kumar, Aditya Prasanna, Jonathan Balkind, Arrvindh Shriraman |
ASPLOS (2) | 2 |