In order to successfully integrate circular economy principles into current value chains, it is crucial to ensure the economic sustainability of disassembly processes. Recent scientific and technological innovations, including Large Language Models (LLMs) in artificial intelligence (AI), are greatly accelerating progress in enhancing robotic capabilities. Dismantling is the first step in the re-manufacturing, repair, and recycling processes of end-of-life (EoL) products. Traditionally, this operation is performed manually by operators or by expensive dedicated robotic cells. Although manual disassembly offers flexibility in handling complex situations, it is a time-consuming and labour-intensive process that can negatively affect the health of operators and the cost-effectiveness of the disassembly process. However, robot disassembly presents difficulties in handling complex parts in a flexible manner. Robot application emerges as an automated versatile solution, capable of handling uncertainties in the frequency, quantity, and quality of end-of-life products. A fully automated approach for the removal of clothing zips from garments is proposed. The approach detects the pixels corresponding to the zip using LLM-Based AI techniques to plan the path of the robotic arm. The solution reduces the effort of AI training in industrial applications. Simulations validate the approach and its performance.

Commercial-off-the-shelf (COTS) multicore systems on chip (SoC) represent a cheap and convenient solution for deploying sophisticated workloads in various application domains. The combination of several CPU cores and dedicated acceleration units tightly sharing memory and interconnect systems can provide tremendous peak performance, but also threatens timing predictability due to memory interference. Even when focusing on main CPU cores only, it has been reported that task slowdown due to memory interference can surpass 10 × . Such poorly predictable timing behaviors bar greater adoption of COTS multicore SoCs in the domain of timing-critical applications, and motivate the wide activity of the research community to study solutions aimed at mitigating the problem. Understanding worst-case interference patterns on such hardware platforms is fundamental for building any effective memory interference control mechanism. A common assumption in the literature is that worst-case interference is generated by (and therefore assessed through) read-intensive synthetic workloads with 100% cache miss rate. Yet certain real-life workloads exhibit worse slowdown than what is generated under said assumed worst-case, so we study the interference effects of both synthetic and real-life benchmarks on different multicore SoCs. Our experiments indicate that cache thrashing causes the worst interference experienced by real-life benchmarks – due to their different usage of caches – and that there is no universal worst-case workload for every platform.

Memory bandwidth contention may severely inflate the execution time of tasks co-running on modern Commercial Off-The-Shelf (COTS) multicores. An effective and widely deployed solution to mitigate the problem is bandwidth regulation , a technique to limit the available memory bandwidth for those cores that are not executing time-critical tasks . The granularity at which time-critical activities can be identified at the core level can be in fact even finer than a whole task, and just span smaller memory-critical section (MCS) therein. As the co-presence of MCS and non-critical task portions in the system dynamically changes over time, bandwidth regulators require more or less frequent reconfiguration of their parameters. Similar reconfiguration techniques thus represent a central component of dynamic Memory Bandwidth Management Schemes (MBMS). In particular, the overhead and latency of such a component determine the feasibility and control granularity of the overall bandwidth-regulation solution. The literature extensively covers low-level bandwidth regulation mechanisms and – to some extent – their integration in wider MBMSs, yet no in-depth analysis is currently available of the impact of reconfiguration techniques . This paper addresses this issue by proposing a comparative analysis of the two basic approaches to reconfiguring bandwidth regulators in a system: synchronous and asynchronous schemes. The analysis, performed on a real-world setup with both synthetic and real-world benchmarks, shows that the asynchronous technique improves the control granularity of a bandwidth regulator by a factor of up to 19x, moving from the ms to the μ s scale.