Timing mismatch between different stages of physical design poses great challenges for circuit optimization to achieve the desired performance, power, and area (PPA) tradeoff. The inaccurate timing estimation prior to routing may lead to over-design with unwanted power and area consumption or iterating back to cell placement at the cost of design turn-around time. Existing learning models could not predict post-routing circuit timing with satisfying accuracy and efficiency due to the limitations of the ignorance of delay correlation along the timing path and the empirical feature selection solutions. In this work, an accurate and efficient prerouting path delay prediction framework is proposed by utilizing a transformer network and residual model with an ensemble feature selection mechanism. Owing to the combined filter and wrapper methods, an ensemble feature selection mechanism is implemented to determine the optimal feature subset based on the timing and physical information at the placement stage for path delay prediction, which is extracted as feature sequences for each cell along the timing path to be trained by transformer network. With the residual model, the predicted timing mismatch between the placement and routing stages by the transformer network is further calibrated to estimate the post-routing path delay. The proposed framework has been validated with ISCAS’85 and OpenCores benchmark circuits for the prediction of post-routing path delay, where the perdition error in terms of relative root mean squared error is limited within 1.3% and 3.0% and the correlation coefficient$R$is higher than 0.999 and 0.995 for seen and unseen circuits, respectively, indicating an error reduction by 2.3–10.6 times compared by prior learning-based models. In addition, the framework achieves average three orders of magnitude speedup compared with the commercial tools and is accelerated by a factor of 14–128 as against the competitive learning models, which is promising to be applied to guide design optimization prior to time-consuming routing stage.

Timing estimation prior to routing is of vital importance for optimization at placement stage and timing closure. Existing wire- or net-oriented learning-based methods limits the accuracy and efficiency of prediction due to the neglect of the delay correlation along path and computational complexity for delay accumulation. In this paper, an efficient and accurate pre-routing path delay prediction framework is proposed by employing transformer network and residual model, where the timing and physical information at placement stage is extracted as sequence features while the residual of path delay is modeled to calibrate the mismatch between the pre- and post-routing path delay. Experimental results demonstrate that with the proposed framework, the prediction error of post-routing path delay is less than 1.68% and 3.12% for seen and unseen circuits in terms of rRMSE, which is reduced by 2.3~5.0 times compared with exiting learning-based method for pre-routing prediction. Moreover, this framework produces at least three orders of magnitude speedup compared with the traditional design flow, which is promising to guide circuit optimization with satisfying prediction accuracy prior to time-consuming routing and timing analysis.

Wide voltage design has been widely used to achieve power reduction and energy efficiency improvement. The consequent increasing number of PVT corners poses severe challenges to timing analysis in terms of accuracy and efficiency. The data insufficiency issue during path delay acquisition raises the difficulty for the training of machine learning models, especially at low voltage corners due to tremendous library characterization effort and/or simulation cost. In this paper, a learning-based timing prediction framework is proposed to predict path delays across wide voltage region by LightGBM (Light Gradient Boosting Machine) with data augmentation strategies including CTGAN (Conditional Generative Adversarial Networks) and SMOTER (Synthetic Minority Oversampling Technique for Regression), which generate realistic synthetic data of circuit delays to improve prediction precision and reduce data sampling effort. Experimental results demonstrate that with the proposed framework, the path delays at low voltage could be predicted by their delays at high voltage corners with rRMSE of less than 5%, owing to the data augmentation strategies which achieve significant prediction error reduction by up to 12x.