Power staple insertion is an effective means to mitigate IR drop in the advanced technology process. Previous works have shown that detailed placement refinement can greatly enhance the power staple insertion rate. However, with FinFET, it is necessary to consider the drain-to-drain abutment (DDA) constraints. We note that extra source node insertion for resolving DDA violations can interfere with power staple insertion. To handle DDA constraints and optimize power staple insertion at the same time, we formulate and solve a new DDA-aware placement refinement problem in this work. Given an initial nonoverlapping placement optimized for other conventional objectives, we compute a refined placement with cell shifting subject to DDA constraints such that the number of staple insertion slots can be maximized. An effective approach is proposed that supports a nonrestricted cell displacement range during placement refinement. It provides the flexibility to adjust the displacement bound of each cell dynamically in order to resolve all DDA violations. As a result, our algorithm guarantees that a placement solution with no DDA violation can always be computed without using a large displacement range for each cell which would require much longer runtime and larger average cell displacement. In addition to cell shifting, we incorporate concurrent cell flipping to reduce the required cell displacement to satisfy the DDA constraints and to facilitate power staple insertion. The experimental results showed the effectiveness of the proposed approach.

Power staple insertion is a new methodology for IR drop mitigation in advanced technology nodes. Detailed placement refinement which perturbs an initial placement slightly is an effective strategy to increase the success rate of power staple insertion. We are the first to address the manufacturing-aware power staple insertion optimization problem by triple-row placement refinement. We present a correct-by-construction approach based on dynamic programming to maximize the total number of legal power staples inserted subject to the design rule for 1D patterning. Instead of using a multidimensional array which incurs huge space overhead, we show how to construct a directed acyclic graph (DAG) on the fly efficiently to implement the dynamic program for multi-row optimization in order to conserve memory usage. The memory usage can thus be reduced by a few orders of magnitude in practice.