Subgraph Graph Neural Networks (GNNs) are emerging as a promising approach to enhance GNN expressiveness, but their more complex graph structures with numerous independent and irregular subgraphs pose significant hardware deployment challenges. In this work, we propose 3D-SubG, a 3D stacked hybrid processing-near/in-memory accelerator for subgraph GNNs. With hybrid bonding packaging technology, a logic die is 3D stacked with a DRAM die for highly parallel memory accesses. The logic die employs digital SRAM-based processing-in-memory (PIM) macros to boost computation density and minimize data transfer. We further propose a bit-level non-zero gathering method to exploit graph sparsity for PIM, a workloadbalanced mapping strategy for subgraph allocation onto different logic-to-DRAM blocks, and a distributed global pooling approach to reduce inter-block data movements. Experimental results show that 3D-SubG achieves average improvements of $146.11 \times$ in performance, $934.18 \times$ in area efficiency, and $1171.80 \times$ in energy efficiency compared to RTX 3090Ti.

The Mixture-of-Expert (MoE) architecture constitutes a significant advancement in the scalability of large- language models (LLMs), achieving better performance compared to traditional dense models with the same size of activated parameters. However, the MoE models introduce two main challenges for their edge deployment: (1) increased memory storage requirements due to the sparse parameter composition and (2) aggravated yon Neumann bottleneck caused by the inherent unpredictability of dynamic expert routing. Recent trends in state-of-the-art MoE models suggest that scaling up both activated and the total number of experts leads to better model performance. However, this multi-expert activated LLM architecture further exacerbates the aforementioned issues. To address these challenges, this paper presents a 3D stacked near-DRAM computing architecture based on available hybrid bonding and mini-TSV techniques, thereby increasing both storage capacity with the same die area and memory bandwidth for MoE models. We also employ 6T-SRAM-based Digital Computing-in-Memory (DCIM) macros as the primary computing components and weight buffers to optimize the effective throughput of LLM inference. Furthermore, we propose a hybrid parallel computation scheme with Greedy-Swap Expert Grouping (GSEG) strategy. It balances the weight-parameter placement between tile groups in 3D-MoE architecture to enhance hardware utilization and overall performance. Through comprehensive benchmarking, the proposed accelerator demonstrates 143.10× and 68.89× speedup in token throughput, and 870.98× and 47.11× improvements in energy efficiency compared to CPU and GPU, respectively, confirming its advantages for multi-expert activated LLM inference.